Abstract
CMOS technologies are widely exploited now in the area of a few-GHz-range radio frequency (RF) circuits as well as in the area of baseband circuits. Accordingly, the CMOS low-noise amplifier (LNA) is gaining its popularity, tailored to the applications such as GSM, PCS, IMT-2000, and wireless LAN. In this paper, compact and comprehensive design strategies for CMOS LNA are presented. Basic topologies are compared and analyzed using key equations newly derived. Using these strategies, an LNA based upon LC resonance using on-chip spiral inductors is designed and investigated. This LNA, targeted for 1.8 GHz PCS, exhibits power gain of about 18 dB and noise figure (NF) of about 2.1 dB by both theory and post-layout simulation under a 0.8-/spl mu/m CMOS process and 3-V supply.
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