Design of 4 bit low power carry select adder

Abstract

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor-level modification to significantly reduce the area and power of the CSLA. Based on this modification 4-bit CSLA architecture have been developed and compared with the regular CSLA architecture. The proposed design has reduced area and power as compared with the regular CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-µm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular CSLA.