Abstract
A tunneling field effect transistor (TFET) attracts attention, because TFET circuits can achieve better energy efficiency than conventional MOSFET circuits. Although design issues, such as the minimum operatable voltage (VDDmin), in ultra-low power MOSFET logic circuits, have been investigated, VDDmin for TFET logic circuits have not been discussed. In this paper, VDDmin of TFET logic circuits is evaluated for the first time, and based on the evaluation, the design guideline is presented for the device engineers of TFET’s that the within-die threshold voltage variation should be reduced as the subthreshold swing becomes steeper.
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