Design, Fabrication and Implementation of Smart Three Axis Compliant Interconnects for Ultra-Thin Chip Stacking Technology

Abstract

This paper reports the current status of a novel MEMS based ultra-high density compliant interconnect technology that was proposed in the last Electronic Components and Technology Conference (ECTC). This MEMS-based interconnect, which we call smart three axis compliant (STAC) interconnects are directly fabricated onto electrical contact pads or thru-silicon vias on die at the wafer-level. These interconnects are initially bound to the die by a chemically soluble release layer. The end of the interconnect is bonded to a contact pad on a package substrate or other die at the wafer level or die level, and the release layer is dissolved to free the interconnect from the substrate, thereby permitting it to accommodate relative displacements. The paper will clearly show successfully fabricated STAC interconnects at 50micron pitch on a silicon die bonded onto an ultra-thin glass die.