DESIGN DIFFERENT TOPOLOGY FOR REDUCTION OF LOW POWER 2:1 MULTIPLEXER USING FINFET IN NANOMETER TECHNOLOGIES

Abstract

The intention of this paper is to reduce power and area of 2:1 multiplexer (MUX) while maintaining the competitive performance. The various configurations are designed using different topology of 2:1 MUX such as CMOS-based MUX, transmission gate and pass transistor using fin-shaped field effect transistor (FINFET). The mobility was enhanced in devices with taller fins due to increase tensile stress. In DG, FINFET can be efficiently used to develop performance and reduce power consumption. In noncritical paths self-determining gate control can be used to join together parallel transistors. We have estimated the optimum power, optimum current, leakage power, leakage current, operating power, operating current and delay in voltage supply 0.7 V at different temperature such as 10°C, 27°C and 50°C, respectively. A 20 ns access time and frequency 0.5 GHz provide 45 nm CMOS process technology with 0.7 V power supply is employed to carry out different topology of 2:1 MUX using FINFET.