Design ASNoC for low-power SoCs

Abstract

This paper proposes a design methodology for application-specific network-on-chip (ASNoC). The methodology can generate optimized hierarchical ASNoC and a corresponding distributed shared memory for different applications. It uses statistical communication traces for cycle-accurate performance analysis for quick evaluation, and is based on floorplan to estimate power and area. The methodology can be easily integrated into current hardware/software codesign flow. Using this methodology, we generated an ASNoC for a H.264 HDTV decoder SoC. We compared the ASNoC with MIT's RAW network in performance, power, and area in detail. The comparison results show that the ASNoC provide substantial improvements in power, performance, and cost compared to regular-topology NoC. In the H.264 HDTV decoder SoC, the ASNoC uses 39% less power, 59% less silicon area, 74% less metal area, 63% less switch capacity, and 69% less link capacity to achieve 2X performance compared to the RAW network.