Design and Verification of Low Power DA-Adaptive Digital FIR Filter

Abstract

A unique pipelined architecture for low-area, low-power, and high-throughput implementation of adaptive filter based on distributed arithmetic (DA) is presented in this paper. Distributed arithmetic (DA) is performed to design bit-level architectures for vector–vector multiplication with a direct application for the implementation of convolution, which is necessary for digital filters. Bit-serial operations and look-up tables (LUTs) are used to implement high throughput filters in which only one cycle per bit of resolution regardless of filter length is used. Also parallel lookup table (LUT) updation. Filtering and weight-update operations are concurrently performed to increase the throughput rate of adaptive FIR filter. The new approach of conditional signed carry-save accumulation is used in place of conventional adder based shift accumulation so that reduction of the sampling period and area complexity is easy. However adaptive DA filters also requires recalculating the LUTs for each adaptation which can nullify any performance advantages of DA filtering. The System is designed in Xilinx ISE 9.1 using Verilog HDL and it is routed using Model Sim 6.3. The Verification of the system's behaviour is done using MATLAB 13. DA adaptive filters are advantageous over digital signal processing microprocessor in terms of total area and power consumption.