Design and Simulation of DPLL for FPGA Based Carrier Recovery Loop: PSK Receiver for Digital Satellite Communication

Abstract

In this paper, we present the digital phase locked loop (DPLL) model for FPGA based carrier recovery loop in Phase Shift Keying (PSK) receiver. The main design goal is to transform S- domain Analog PLL to the Z-domain of DPLL without redesigning model. Additionally, this paper present design, analysis, mathematical modelling, mathematical analysis of algorithms which are Impulse-Invariance Algorithm (IIA), Zero-Order Hold Algorithm (ZOHA), Bilinear Transform Algorithm (BLTA) and Matched Pole-Zero Algorithm (MPZA). Design of DPLL which is based on all discretization algorithms are presented and simulated using MATLAB 13a and Xilinx ISE 14.7 system generator. We present the comparative analysis of simulation from which it is found that BLTA is the most celebrated algorithm. Moreover, The BLTA based structure of DPLL adapts the response to allow the DPLL to lock faster than other discretized DPLL. Analysis and steps of the discretization algorithms is discussed and results of MATLAB and Xilinx ISE 14.7 system generator are presented for FPGAs and ASICs based platform.