Design and simulation of a 65 nm Macro-Pixel Readout ASIC (MPA) for the Pixel-Strip (PS) Module of the CMS Outer Tracker Detector at the HL-LHC

Abstract

The MPA is the pixel readout ASIC for the hybrid Pixel-Strip module of the Phase-II CMS Outer Tracker upgrade at the High Luminosity LHC (HL-LHC). It employs a novel technique for identifying high transverse momentum particles and provides this information at 40 $MHz$ rate to the L1-trigger system. The chip also comprises a binary pipeline buffer for the L1-trigger latency, and a data path to support the readout of full events with a maximum trigger rate of 1 $MHz$ and a latency of 12.8 $\mu s$. The design and implementation in a 65 $nm$ CMOS technology of the first prototype ASIC that integrates all functionalities for system level operation with a power density lower than 90 $mW/cm^2$ are presented in this contribution.