Design and optimization of high-performance resilient network-on-chip based multiprocessor system-on-chip

Abstract

As feature sizes continue to shrink with the advancement of nanotechnology, multiprocessor system-on-chip (MPSoC) becomes a promising solution to satisfy the growing demands of future complex applications. Network-on-chip (NoC) can effectively improve the scalability and lower the power consumption of MPSoC, and it is replacing traditional bus as the major MPSoC communication architecture. In this thesis, I study NoC-based MPSoC design and optimization methods to improve MPSoC performance and reliability. Given an MPSoC application and hardware architecture, the challenges are mapping the application tasks onto available processor cores, scheduling the task executions, and allocating memory resources to the application tasks to optimize system performance and hardware utilization. Formal methods, including satisfiability (SAT), satisfiability modulo theories (SMT) and model checking (MC), are studied, and sophisticated search space reduction techniques are proposed to significantly improve the performance. The proposed techniques are applied to a novel NoC-based MPSoC architecture, called sensor-network-on-chip (SENoC). SENoC can collaboratively monitor the chip reliability and guarantee correct and efficient executions of MPSoC applications under soft errors and power gating induced power/ground noises. To facilitate NoC-based MPSoC evaluations, I develop a benchmark suite based on realistic MPSoC applications.