Design and optimization of a low-power dynamic MCML-based phase-frequency detector using Taguchi DoE and ANOVA for frequency synthesizers with fast-locking of 0.5 μs

This paper presents the design of a novel Phase Frequency Detector (PFD) and Charge Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our proposed PFD technique can eliminate the effect of missing edge and phase ambiguity problems in conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and charge injection error problem with this new design technique. The design charge pump current mismatch has been checked in 0.13 µm CMOS process and worst case mismatch error is 0.025 µA for a control voltage range from 0.25 V to 1.0 V for a 1.2 volt supply voltage. Phase noise performance of the proposed PFD and CP circuit is about −117.3 dBc/Hz at 1 MHz offset frequency for a load capacitance of 10 fF. Current noise of our PFD and CP circuit has been measured from the transistors level simulation to find the phase noise of the fractional-N PLL, for output frequency of 2.2 GHz with 40 MHz reference signal in CppSim system simulator. Proposed PFD and CP switching circuit's phase noise performance shows the 17.36 dB improvement compare to the NOR based PFD and 7.4 dB improvement compare to the NAND based PFD topology. Also, the effect of CP current mismatch and dc offset current at any of the current source or sink has been incorporated to check the effect on spur and phase noise of the fractional-N frequency synthesizer. In addition, charge pump current noise and phase noise modelling has been done here to find the output phase noise of the PLL considering the PFD and CP output current noise measured in transistor level in 0.13 µm CMOS.

Problem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for zigbee. This study discussed designing one of the blocks of zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for zigbee as it is meant to be a low cost communication system. Phase Locked Loop is responsible on carrier frequency selection in a communication system. It is the most power consumer block in the transceiver as well. The objective of this study was designing a low power fully integrated integer-N PLL frequency synthesizer targeting the 2.4 GHz band IEEE 802.15.4 Std zigbee. Approach: Minimizing total power consumption of PLL was achieved by introducing a novel design of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. The proposed PFD used only 12 transistors and it preserved the main characteristics of the conventional PFD with a simple architecture. The Charge Pump (CP) was single-ended source switch to save power and minimize mismatches. The Voltage Controlled Oscillator (VCO) spans from 4.737-4.977 GHz band using LC resonator. The VCO worked at double the frequency band to avoid local oscillator leakage and feed through. The integer N divider used a 15/16 dual modulus. Results: The proposed PLL was designed using Silterra 0.18 um CMOS process. It consumed 3.2 mW with 1.8 voltage supply. Phase noise is-113.4 dBc Hz-1 at 1 MHz. The proposed PFD works up to 2.5 GHz with free dead zone. The Charge Pump (CP) works with 20 uA, lock-in time is 27 us and total die area is 1×2 mm. All results were taken from extracted layout simulations. Conclusion: The results of this study indicated that a PLL can work with less power consumption and save the transceiver battery. The proposed PFD was suitable for high speed applications.

The design of Low Power Low Glitch Dynamic Phase Frequency Detector (PFD) is proposed in this paper. The dynamic PFD helps Delay Locked Loop (DLL) to detect the phase error information in form of pulses at high frequency and plays an important role for improving the performance of complete DLL block. A Low Power and Low glitch phase frequency detector is proposed at 180 nm technology node using GPDK180 library with supply voltage VDD=1.8 V in Cadence Virtuoso for schematic composer, Spectre tool for simulations and Cadence Layout editor for layout. By simulating the proposed PFD block, significant reduction in area and power dissipation was observed. Also phase sensitivity has improved significantly and there is no reset path present. It was observed that the proposed dynamic PFD has very low glitch as compared to conventional D flip-flop based PFD. This PFD is designed for low power Delay Locked Loop.

This article introduces a high-speed phase frequency detector (PFD). In the proposed circuit, a two-stage reset-free PFD based on current mode logic (CML) is introduced. The two stages of the proposed PFD were the input and detector stages. The detector stage determined the UP and DOWN signals, accurately identifying the phase difference between the reference and feedback signals. This design has no reset path, which ensures that it operates without dead zones. To evaluate circuit robustness, the process, voltage, and temperature (PVT) tolerance levels were analysed. Different corners (TT, FF, SS, FS and SF), voltages (0.8, 1, 1.2 V) and temperatures (40, 27 and 90°C) are verified. The power consumption and propagation delay are 11.57 μW and 3.06 ps, respectively, with the power delay product of 35.39 fJ. The output and phase noise are −149. 31 dB and −160.54 dBc/Hz, respectively, with a frequency of 6.69 GHz. The simulations were performed using a Cadence virtuoso in 45 nm CMOS technology. The results were verified using a Monte-Carlo analysis with 200 samples. The results clearly show that the two-stage CML PFD is highly tolerant to PVT and appropriate for high-speed frequency synthesiser applications.

Phase frequency detector (PFD) is used for phase detection in the phase lock loop (PLL) and always active. PFD operates at higher frequencies and consumes more power. To minimize overall power of PFD, design and implementation of power efficient PFD which operates at higher frequencies are discussed in this paper. To reduce low-power consumption of PFD, the techniques such as pass transistor logic, adaptive voltage level, and removal of the reset path are proposed. The proposed PFD operates up to 2 GHz whereas the PFD without reset path can function at higher frequencies too. The existing and proposed low-power PFDs have been designed and implemented using Cadence Virtuoso in CMOS 180 nm technology and simulated using Cadence Spectre.

Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops

Design and optimization of phase frequency detector through Taguchi and ANOVA statistical techniques for fast settling low power frequency synthesizer

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

This study presents a new CMOS dynamic Phase Frequency Detector design (PFD). The suggested PFD circuit (PPFD) has been developed, simulated, and the results have been examined. Internal signal routing is used in the PPFD circuit to reduce dead zone. A Loop-filter is nothing but the Low Pass Filter (LPF) integrates error current to generate VCO control voltage and suppresses the noise and unwanted phase detector outputs. Overall, the PLL is configured in 0.18 µm CMOS technology with a T-spice environment and it is then connected with the frequency divider circuits (FD/2 & FD 2/3). From the comparisons, it shows that the low power consumed is about 0.65 µW for the PLL with FD2/3. In addition, Monte Carlo simulation is performed for the PLL circuits and the power values are analyzed. In order to extend the research work, Pass transistor logic based FDs can be used to reduce power.

Recent development in VLSI and CMOS technology has led to numerous power reduction techniques. This edge has helped in the implementation of the Phase Locked Loop (PLL) for wireless communication applications. The first block of a PLL structure is the Phase Detector which acts as a bottleneck to the entire system thereby affecting the speed and performance of the PLL. Phase Frequency Detector (PFD) operates at very high frequencies and consumes more power. Two low power PFD architectures are proposed in this work. The proposed-1 PFD uses Inverter and two input NAND gate with LECTOR technique to reduce leakage current. The proposed-2 PFD uses a Double edge triggered D-flip-flop with pulse-clocked and TSPC logic which consumes the least power among all the implemented architectures and also requires less transistors. The PFDs circuits are implemented in CMOS 180nm technology using Cadence Virtuoso and simulated in Cadence Spectre with 1.8V supply voltage and operating frequency at 20 MHz. Performance of reference and proposed PFD circuits are analyzed w.r.t. to power and area (transistor count). The results inferred reduction in the power consumption when compared to reference architectures and operate at higher frequency.

High-speed phase frequency detector (PFD) is one of the key module for high-frequency phase locked loop (PLL) systems. The performance of PLL depends on the operation of PFD. This paper presents a new PFD design in 0.18μm CMOS technology using 3T XOR and 3T NAND gates. Supply voltage has been varied from 1.8V to 2.4V in the proposed design. The new PFD consumes power within a range from 505.78μW to 1310.80μW when operating at 500 MHz clock frequency. Results have been compared with conventional MOS current mode logic (MCML) design and the proposed design shows less power consumption. The proposed PFD is a useful circuit for low power and high-speed PLL systems.

In this paper, we present the analysis of the conventional phase detector (PD) and phase frequency detector (PFD). Then, we have proposed the modified PFD using D-Flip Flop (DFF) based on true single-phase clock (TSPC) topology. The conventional PFD generates the UP/DN signal with respect to the phase difference between the two inputs. However, the proposed technique of immediate reset path improves the operating frequency in the order of 1.5 MHz–2.4 GHz. Also, it shows the minimum power consumption as compared with the traditional PFD architecture @ 416. 83 µW. Along with this, it shows the improvement in terms of phase noise i.e., –102.3 dBc/Hz at 1 MHz offset frequency. The design is simulated in a standard 0.18 µm CMOS technology node with a 1.8 V supply voltage. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL applications such as Zigbee, Wi-Fi, and Bluetooth.KeywordsPhase Detector (PD)Phase Frequency Detector (PFD)Phase noiseHigh speedPhase Locked Loop (PLL)

A design of a 5.6 GHz frequency synthesizer with switched bias LIT VCO and low noise on‐chip LDO regulator for 5G applications

Delay Locked Loops (DLL) adapted in various applications due to its low power characteristics. Aggressive power demand in sensors, medical devices and new communications applications with embedded DLL has affected by Phase Frequency Detector (PFD) design techniques. This paper presents a review of various PFD in DLL design based on their main parameters including dynamic logic PFD topologies, PFD important parameters and issues total power consumption as well as their design trade-offs. This review paper gives a guideline to the future researchers for designing high speed and low power PFD.

High-performance phase frequency detector (PFD) is an integral part of the high-speed phase-locked loop (PLL), and their characteristics have a great impact on the performance of PLL system. The demand for the decreasing of power dissipation in CMOS design is a major challenge to optimize the circuit power consumption. In this paper, the concept of low power techniques namely, stacking and body bias have been utilized for the implementation of the proposed CMOS PFD for high-frequency applications. All the results related to the proposed designs have been obtained using TSMC 0.18 µm CMOS process. The proposed PFD design shows a remarkable reduction in power dissipation up to 172.670 pW which is significantly lower than the conventional PFD. Simulation results also show that the proposed design has wider operating frequency of 1 GHz, making it a suitable circuit for high-performance PLL systems.