Design and Implementation of Power Efficient Encoder for Transition Reduction in Off-Chip Buses Using Adaptive Bus Encoding Technique

Abstract

This paper deals with the design and implementation of power efficient encoder for transition reduction in off chip buses using ABE (Adaptive Bus Encoding) technique. In both the embedded and high performance systems, the effect of power consumption is becoming highly prominent, whereas the off-chip data buses remains to be a considerable power consumer. In most cases, the input data streams are not known because of the fact that the data streams are more random and less sequential. With subject to this, the adaptive bus encoding (ABE) mechanism is introduced which is executed without the preliminary knowledge about the required input streams. The proposed methodology of this paper make use of the spatial redundancy for the prevention of data loss while recovering them. This ABE framework reduces the transitions in highly capacitive off-chip buses and also this technique is associated with the power dissipation in the off chip buses for the significance of power efficiency and high speed communication. Thus, it minimises the extra dynamic power consumption due to the encoding circuitry mechanism.