Design and Implementation of Online Clock Skew Scheme-based Asynchronous Wave-pipelined Distributed Arithmetic Filters on FPGA

Abstract

In this paper, Design and implementation of asynchronous wave-pipelined (WP) Distributed Arithmetic (DA) Alters on FPGA using online clock skew scheme is proposed. DA Alters of 8-taps, 16-taps, and 32-taps are implemented on an FPGA using non-pipelining (NP), pipelining, and WP schemes and compared with that of self-tuned scheme reported in the literature. The WP DA filters operate 1.4 to 1.53 times faster than NP DA filters. The delay-power products of the WP DA filters of 8-taps, 16-taps, and 32-taps using Online Clock Skew Scheme are less by 51.24%, 29.6%, and 3.78%, respectively, compared to those using Self-tuned Scheme.