Design and Implementation of MAC with Time-Sensitive Networking

Abstract

According to the requirements of Time-Sensitive Networking (TSN) [1] in applications, this paper proposes a method to implement TSN technology in engineering, and designs a MAC with TSN technology, which consists of a data receiving MAC controller, a transporting MAC controller, a data processing unit, a frame classification and hash lookup unit The module consists of a data receiving MAC controller, a transmitting MAC controller, a data processing unit, a frame classification unit and hash lookup unit, a Crossbar switching unit, a processing unit, a time synchronization and management unit, an 8-priority shared cache queue manager and a scheduler. The scheduling algorithm of this module is implemented using the gated scheduling algorithm and the frame preemption traffic scheduling algorithm, and the algorithm implementation mechanism and scheduling process of the adopted traffic scheduling algorithm are described in detail. In this study, the MAC module is designed using Verilog hardware description language, and The key circuits and the circuits with design risks were evaluated and analyzed, furthermore the final design of MAC module with time-sensitive network was realized. And by using SystemVerilog to write simulation code, the key functions are simulated and verified by FPGA. This study realizes the integration of TSN technology into the MAC module, which mainly solves the problems of time synchronization, data scheduling and system configuration in the MAC, and the MAC module has the features of high integration and high time synchronization accuracy.