Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm

Abstract

A dual-stage hardware architecture that supports two kinds of moving averages for the on-line clustering algorithm is proposed. The architectural design of this work is different from the one of previous works that focus on the iterative clustering algorithm. The system includes a set of memories that operates in ping-pong mode, so that the Manhattan distances can be computed when the centroids are updated. The high-throughput parallel divider in the moving-average engine is a new solution to reduce the computational time of one division operation to a single clock cycle and to calculate cumulative moving averages with no precision loss. Two hardware examples show the robustness of the proposed architecture, and the architectural analysis is performed with the 90 nm CMOS technology. In the first example, the gate count is the smallest and the normalized power consumption of this work is the lowest among previous works. In the second example, the architecture is compared with related works, which implement the Self-Organizing Map (SOM) algorithm. The proposed work has high flexibility for parameter combinations and can achieve high performance for color quantization in a single iteration. The functionalities of the proposed system are also verified with the background subtraction application.