Design and implementation of FPGA-based hardware acceleration system for target detection

Abstract

Since the application of target detection in convolutional neural networks is becoming more and more widespread, and the computational volume is increasing, the complexity of the network hierarchy and the memory requirements are gradually increasing, so according to the Field Programmable Gate Array (FPGA) parallel computing characteristics, using FPGA to accelerate the convolutional neural network hardware, can design a CPU+FPGA target detection hardware acceleration system. The system adopts the YOLOv2 target detection algorithm and divides the tasks according to the network structure of the algorithm, and at the same time, it quantifies the 32-bit floating-point numbers of the algorithm with 16-bit fixed points, optimizes the convolutional, pooling, and reordering layers of the algorithm, and finally designs the algorithm by using the HLS high-level synthesis. The system uses PYNQ-Z2 platform to implement the convolutional neural network YOLOv2, and the final system performance reaches 27.06GOPs (Giga Operations Per Second, 1 billion operations/s), and the power consumption is only 2.609W, compared to CPU (E5-2620V4), its performance is 6.58 times that of CPU, and the power consumption is only 3% of the CPU, which has certain advantages compared with current target detection systems.