Design and implementation of FIR lattice filter using floating point arithmetic in FPGA

Abstract

The floating point arithmetic process is the common operation in numerous processors. The floating point adder process is the complex operation as compared to the multiplication as it consists of latency, area dependent sub operations. Now a days, digital companies concentrating on FPGA in place of ASIC's as it is effective with reference to, time to market, flexibility and low cost. The floating point adder implemented using Leading One Predictor (LOP). This technique is used to improve the performance of the floating point adder in terms of area, delay and speed of operation. The multiplication of two floating point numbers is also important in Digital Signal Processor and it is implemented by using generic multiplier. To keep all design properties in an unlocked state, we kept design goal strategies in a balanced mode so that area, delay and speed are always balanced. The adder, multiplier and delay are the basic building blocks in the design of digital filter structure. The implemented floating point adder and multiplier in single precision format and double precision format are used to design FIR lattice filter structure. The aim of this paper is to analyze the different hardware module used for the implementation of floating point adder and multiplier algorithm using Very high speed integrated circuit Hardware Description Language (VHDL) and their synthesis for Xilinx Virtex-5 XC5VLX50T device using Xilinx integrated software environment 14.2.