Abstract
A 64 kbit bubble memory chip is designed, fabricated, and tested. The chip contains 128 minor loops, each with 513 bits. The circuit period is 20 µm. The chip size is 6.4 mm by 6.0 mm. The bubble material used is (YSm)3(FeGa)5O12 with a demagnetized strip width of 4.5 µm. The chip is mounted in a memory module and tested by a chip tester at a rotating field frequency of 100 kHz. Complete memory operations are successfully performed using all memory addresses of all minor loops and an overall bias margin of 10% is obtained. Thus, the feasibility of practical 64 kbit memory chip operation is confirmed.
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