Design and Comparative Analysis of Dynamic Comparators for SAR ADC

Abstract

AbstractDeveloping a low-power dynamic comparator for SAR ADC is one of the emerging research domains for biomedical applications. Designing, simulation, and comparative analysis of different dynamic comparators in 45 nm technology node of CADENCE Virtuoso are considered in this research work. The paper includes an analysis of delay and power with varying supply voltage for designed dynamic comparators in mentioned 45 nm technology node. Simulation analysis has validated that at the minimum applied voltage (Vdd) of 0.4 V, the circuit delay has been decreased from 172 ns in conventional comparator to the value of 249 ps in double tail dynamic comparator. Further, analysis has observed a reduction in power from 13.3 pW in conventional comparator to 4.7 pW in double tail dynamic comparator at operating supply voltage (Vdd) of 0.4 V. Also, the power analysis of different designed dynamic comparators has been carried out with the increase in supply voltage (Vdd) up to maximum of 2 V. Simulated results have shown that with increase in supply voltage (Vdd), the corresponding delay of designed dynamic comparators has decreased with increase in the power dissipation.KeywordsAnalog to digital converterClocked comparatorsConventional comparatorDynamic double tail comparator