Design and characterization of the FAST chip: a front-end for 4D tracking systems based on Ultra-Fast Silicon Detectors aiming at 30 ps time resolution

Abstract

Detectors able to measure the time of flight with very high accuracy (∼10 ps RMS) are becoming fundamental in the design of new High Energy Physics experiments, where accurate time measurements will be used to mitigate pileup effects. The development of such detectors has spurred intense R&D in both silicon sensors and the associated readout electronics, aiming at obtaining silicon-based detectors with a time resolution in the few tens-of-picosecond range. This work presents FAST, a family of three different 20 channel amplifier-comparator chips, tailored to the readout of Ultra Fast Silicon Detectors. These ASICs have been designed optimizing the sensor-readout interplay with the aim of reaching the smallest possible jitter term. The three chips of the FAST family differ in the architecture of the front-end while sharing the channel back-end, consisting of a leading-edge discriminator and a LVDS driver. The goal of these front-ends is to achieve a time resolution of about 30 ps RMS while coupled to a sensor with a few pico-Farad capacitance, keeping the power budget of the single channel below 1.3 mW. This paper reports the description of the FAST design architecture and summarizes the results on the initial characterization of one chip of the FAST family, in a stand-alone test structure and when coupled to a UFSD.