Design and Characterization of Area-Efficient Trench Termination for 4H-SiC Devices

Abstract

In this paper, the operation mechanism of trench termination is investigated through 2-D numeric simulation on Silvaco. It is found that in trench termination, the electric field is terminated by the accumulated holes at the outer trench sidewall. In order to ensure a high termination breakdown voltage, the trench is refilled with a combination of SiO2 and polyimide (PI). Through various 2-D numerical simulations, the impact of structural parameters on breakdown voltage has been discussed, namely, trench depth (TD), trench width (TW), and sidewall tilt angle. The 3-D simulations are also conducted to investigate the effect of round corner radius on the device breakdown voltage and electric field in the dielectrics. Based on these results, the trench termination is designed and then fabricated along with a p-i-n diode. The measurement results show that a $14~\mu \text{m}$ wide trench is sufficient to terminate a voltage of 1750V (>96% of the ideal planar breakdown). Comparing with conventional field limiting rings junction termination extension (FLR/JTE) technology, this trench termination can significantly reduce the termination length by a factor of 4. As a result, the area efficiency is largely improved from 62% to around 90% for a 2A device conducting at 1000 A/cm2. These results indicate that the SiC device price can be substantially lowered with such an area-efficient trench termination technology. Furthermore, the 168-h high-temperature reverse bias (HTRB) test under 1200 V and 175 °C shows the potential of this trench termination for long-term reliable operation. Finally, unclamped inductive switching (UIS) tests have been conducted on fabricated devices. Compared to commercial SiC junction barrier Schottky diodes with FLR, fabricated p-i-n diodes with trench termination show significant higher avalanche capability.