Design and analysis of wide tuning range differential ring oscillator (WTR-DRO)

Abstract

A new circuit of delay cell for differential ring oscillator (DRO), to generate wide tuning range, has been proposed. Two architectures of DRO: 3 stage and 4 stage, have been designed and simulated under the power supply constraint of 1.1 V, using GPDK 45 nm CMOS technology. Dual voltages are used to control the tuning frequency range in 3 stage DRO whereas single voltage control is used in 4 stage DRO. Tuning ranges of 351 MHz–30.33 GHz and 574 MHz–20.49 GHz, are generated using the proposed 3-stage and 4-stage DRO circuits, respectively. Total Harmonic Distortion of both circuits, is also measured through simulation. Power consumption of the proposed 3-stage and 4 stage DRO, are found to be 866 μW and 783 μW at an oscillation frequency of 2.77 GHz and 1.86 GHz, respectively. Proposed circuits exhibit phase noise of − 96.7 dBc/Hz and − 99.54 dBc/Hz at an offset of 10 MHz from the frequency of oscillation. Layout, is also drawn, occupies an area of 137.97 μm2 and 170.34 μm2 for 3 stage and 4 stage DRO, respectively. Robustness of the proposed circuits are verified across Process, Voltage and Temperature variations. The proposed DROs exhibit the largest tuning range when compared with the recent literature.