Design and Analysis of Improved IGBT with Embedded p+ in N-Buffer Layer

Abstract

In this paper, the superjunction IGBT with embedded p+ in N-Buffer layer is proposed along with the gate engineering technique. The hybrid p+ section in N-Buffer layer, provides extra injection of the minority charge carriers in the drift region in order to modulate collector current density (J C ). This enhancement in J C is further improved by the thin gate oxide near n-source region, results in enhanced electric field and hence improving the conductivity. 11% improvement in J C is observed for proposed device with respect to the conventional one hence reducing specific ON-resistance by 10%. In addition to this, broad oxide layer is also provided at the bottom side of the gate, which reduces the extra charge carrier accumulation closed to bottom gate surface and helps the proposed device to turn-off quickly. The improved turn-off time and delay time minimizes the energy losses (E off , E on ) of the proposed device. The reduction in E off and E on is obtained as 33.23% and 35.42%, respectively, at 1.36V of on-state voltage drop (V on ). Additionally, proposed device also shows the improvement in Baliga’s Figure of merit (BFOM) and industrial FOM (FOM1) by 13% and 115% as compared to conventional device.