Design and Analysis of Address-Adaptive Read Reference Settings for Multilevel Cell Cross-Point Memory Arrays

Abstract

Multilevel cell cross-point memory arrays can be used to architect high-density resistive memory. However, coupled sneak current and IR drop cause cell-to-cell nonuniformity of multilevel readout current in cross-point memory arrays during read operations. To eliminate sneak currents along the selected bit-lines (BLs) and regulate sneak currents along the selected word-line (WL), we design unselected WL grounding, unselected BL partial-biasing parallel read scheme. Then, we analyze the impact of the partial-bias coefficient on effective read voltage and array power consumption. We observe that multilevel readout currents are only sensitive to BL location. Therefore, to improve the array-level multilevel read margins, we further propose a BL location-adaptive multilevel read reference setting scheme that groups adjacent BLs and shares the multilevel references in a fine-grained fashion. We also analyze the impact of reference sharing granularity, IR drop coefficient, resistance ratio, and the number of resistance states per cell on the array-level multilevel read margins. SPICE simulation shows that sharing multilevel read references across the entire cross-point array with the size of 512 $\times $ 512 can only distinguish 12 resistance states, whereas our design can distinguish all the 16 resistance states throughout the array and can improve the normalized array-level read margin from −1.04 to 0.23.