Demonstration of a Ternary Inverter Based on the Novel TDDFET With Dual-Doped Source and Asymmetric Gates

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high I/sub on//I/sub off/ ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased I/sub on//I/sub off/ ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require V/sub g/=V/sub d//2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.

In this paper, we investigate the impact of underlap channel, affecting the performance of 20 nm channel length Schottky barrier (SB) double-gate metal-oxide-semiconductor field-effect-transistors (SB-DGMOSFETs) using 2D ATLAS TCAD simulation. For this purpose, we proposed an asymmetric underlap channel double gate (DG) SB-MOSFETs with Si 3 N 4 spacer layer. Simulation of major device performance metrics such as on-state current (I ON ), off-state current (I OFF ), subthreshold slope (SS), threshold voltage (V th ), and associated capacitance variation gate-to source capacitance (C GS ), gate-to-drain capacitance (C GD ) have been done for substrate thickness (T Si ) ranging from 6nm to 10nm. It has been found that by employing underlap channel there is improvement in I ON , reduction in I OFF & ambipolar leakage current. However, the reduction in ambipolar behavior is also observed, due to reduced effective gate voltage across the underlap channel length.

In this paper, asymmetric gate oxide and source pocket double-gate tunneling FET (DG TFET) structure is proposed to enchance the current drive. Compared with conventional DG-TFET, the propsed TFET has steeper average subthreshold swing (SS), larger on currents, smaller supply voltage. The resason of improvements is mainly attributed to the enhanced tunneling electric field high-k gate oxide brings and larger tunneling area cuased by the source pocket.

In this research article, we optimize the design metrics of InP (Indium Phosphate) HEMT (High Electron Mobility Transistor) using asymmetric gate recess and multi-layered cap. The device proposed in this paper possesses heavily doped Source/Drain (S/D) region, asymmetric gate recess, multi-layered cap region, InP layer between cap and buffer region. The proposed device incorporates the use of ‘T’ shaped gate and δ (delta) - doping technique. This paper analyzes the RF and DC performances of the device with an In0.52Al0.48As supply layer, In0.65Ga0.35As channel layer built on an InP substrate, with a delta doping of thickness 1 nm, cap layer with varying compositions of InGaAs and a heavily doped S/D region of In0.52Ga0.48As. Complete analysis of the device such as its output characteristics (Drain Current (ID) – Drain Source Voltage (VDS)), transfer characteristics (ID − Gate Source Voltage (VGS)), threshold voltage (from ID - VGS plot), transconductance and transition frequency (fT) are obtained at room temperature (300 K) and the obtained values of these parameters are better as compared to the conventional HEMT because of the abatement of parasitics like S/D resistances. All simulations are performed using Silvaco ATLAS.