Abstract
Nowadays a high-level integration with unprecedented functionality and efficient performances is achieved through 3D packaging techniques known as System-In-Package (SIP). The paper describes the reduction process conducted on a realistic SIP module case in order to establish a behavioral thermal network having a large number of power sources. Besides this device has been slightly modified to focus on the recent 3D integration techniques such as the stacking of chip, multi-chips side by side architecture or the embedding of conventional individually-packaged Integrated Circuits (IC). These works compared the prediction of a DELPHI style Compact Thermal Model (CTM)[1][6] to a numerical Detailed Thermal Model with for aim to illustrate the diminution of computation delays, the expected accuracy and some efficient ways to improve it. Then it describes the performance of a novel methodology that nests a set of Sub-Compact Thermal Models (SCTM) within the detailed numerical model, far less grid-intensive, and its ability to preserve the final SIP CTM quality.
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