Delay and noise estimation of CMOS logic gates driving coupled resistive–capacitive interconnections

Abstract

The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive–capacitive interconnect lines is presented in this paper for different signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate are presented for a variety of signal activity conditions. The uncertainty of the effective load capacitance on the propagation delay due to the signal activity is also addressed. It is demonstrated that the effective load capacitance of a CMOS logic gate depends upon the intrinsic load capacitance, the coupling capacitance, the signal activity, and the size of the CMOS logic gates within a capacitively coupled system. Some design strategies are also suggested to reduce the peak noise voltage and the propagation delay caused by the interconnect coupling capacitance.