Abstract
A hybrid model for CMP process recipe and IC design optimization is introduced. It combines data mining techniques, CMP physical aspects, and uses existing CMP metrology data. The model has been validated to within 7% of the actual thickness measurements on a test chip, and the simulated topography profiles closely match those measured by an AFM. The hybrid model provides intermediate results for all the process steps, including ECD, bulk, touchdown and barrier removal and runs an order of magnitude faster than physical based model. The calibrated hybrid model has been used for wafer level CMP hotspots detection, CMP process recipe change, optimization, dummy fill generation, and rule file development. A novel CMP metal fill tool is also developed to incorporate a field solver for critical nets RC parasitic and timing impact estimation, and a mechanical model for ultra-low k dielectric mechanical strength consideration in addition to a hybrid model.
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