DA-Based Efficient Testable FIR Filter Implementation on FPGA Using Reversible Logic

Abstract

This paper discusses the FPGA implementation of finite impulse response (FIR) filters using a testable reversible logic-based design. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up table (LUT) accesses. The canonical signed digit (CSD) representation is used to represent the coefficients which are compared with sum-of-powers-of-two (SOPOT) technique of coefficients representation. Distributed arithmetic provides a multiplication-free method for calculating inner products of fixed-point data, based on table look-ups of pre-calculated partial products. The implementation results are provided to demonstrate a high-speed and low power proposed architecture. The proposed filter is implemented in very high speed integrated circuit hardware description language (VHDL) and verified via simulation. The reversible architecture scheme yields significantly reduced complexity, low power, and high speed features. The major concern with reversible gates is the reduction of garbage outputs and constant inputs. The proposed gate has less garbage outputs and constant inputs, which are important parameters for reversible designs. The proposed method offers average reductions of 30 % in the number of LUT, 42 % reduction in occupied slices and 38 % reduction in the number gates for low pass FIR filter implementation method. The proposed design shows 45 % improvement in performance as compared to existing one.