Current source transistor optimization methodology for noise optimized charge sensitive amplifier with fast shaper

Abstract

In this paper, we discuss the noise contribution of the current source transistors in the charge sensitive amplifier for application in the front-end semiconductor radiation detectors. We developed an analytical methodology that allow to determine the optimum geometry for the current source transistors, so that the current source transistor ends up contributing only a fraction of the input transistor noise in the charge sensitive amplifier. The proposed methodology ensures that the input transistor noise becomes a dominant factor in the amplifier, thus making the known input transistor noise optimization methodology easily applicable. The example charge sensitive amplifiers based on the dual PMOS cascode amplifier structure have been designed by adopting the proposed current source optimization methodology, and next have been simulated using the IBM CMOS 130nm technology. The proposed optimization methodology has been found in good agreement with simulation results using deep submicron CMOS technology.