Crosstalk reduction in copper on‐chip interconnects with graphene barrier for ternary logic applications

Abstract

SummaryThis paper presents the investigations of crosstalk effects in ternary logic‐based coupled interconnects. The crosstalk analysis is investigated for coupled copper interconnects and copper‐multilayer graphene (Cu‐MLG) interconnects. In Cu‐MLG interconnects, the Cu interconnect is enclosed with MLG barrier and standard ternary inverter is used to drive the interconnect. Based on the industry standard HSPICE simulation results, the crosstalk effects such as noise peak and delay are lower compared with conventional Cu interconnects. Moreover, the Cu‐MLG interconnects show reduced power dissipation, power delay product (PDP), and energy delay product (EDP) over the Cu interconnects. From the simulation results, it is observed that the Cu‐MLG interconnects provides the performance improvements up to 30.67% compared with the Cu interconnects. Thus, the Cu‐MLG interconnects are more compatible for ternary logic integrated circuits compared with traditional Cu interconnects.