Cross-sectional specimen preparation from ICs downside for SEM and TEM-failure analyses using focused ion beam etching

Abstract

A procedure is presented of the cross-sectional preparation of locally well-defined areas in flip-chip packaged IC structures. Using mechanical and ion milling techniques, the silicon substrates are thinned from their bottom to optical transparency to observe the layer stack structure without damaging the active substrate areas. The IC layout is compared to optical images of the IC structures, which are taken of the downside of the chip. These images are used for the precise positioning during the cross-sectional preparation by means of the wire saw and the focused ion beam technique (FIB). The combination of conventional preparation techniques with optical microscopy and ion milling enables the preparation of transistor structures, conducting path 2, conducting holes as well as bonded interconnections in marked positions from the downside of ICs and their investigation by scanning (SEM) and transmission electron microscopy (TEM).