Abstract
In this article, the physico-chemical and electrochemical conditions of through-silicon via formation were studied. First, macropore arrays were etched through a low doped n-type silicon wafer by anodization under illumination into a hydrofluoric acid-based electrolyte. After electrochemical etching, ‘almost’ through-silicon macropores were locally opened by a backside photolithographic process followed by anisotropic etching. The 450 × 450-μm² opened areas were then selectively filled with copper by a potentiostatic electrochemical deposition. Using this process, high density conductive via (4.5 × 105 cm−²) was carried out. The conductive paths were then electrically characterized, and a resistance equal to 32 mΩ/copper-filled macropore was determined.
Highlights
Nowadays, the scaling down of devices is coming to an end
The first part of the present paper describes the different strategies to achieve conductive through-silicon via (TSV) from ordered macroporous silicon
To determine the copper growth homogeneity and the localization efficiency, silicon was selectively etched by a KOH solution at high temperature (80 °C)
Summary
The scaling down (known as ‘More Moore’) of devices is coming to an end. To maintain a constant evolution of the device performances in the future, alternative ways must be explored. The 3D integration is based on the use of the semiconductor volume to connect both sides of a silicon wafer [1,2]. This technique enables the stacking of the dies and leads to an important surface gain. The through-silicon via (TSV) technology is the key parameter for 3D integration allowing through-silicon connections. This technique is based on the etching of TSV and the filling of these through holes by a conductive metallic material such as copper or tungsten [1]
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