Abstract
Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect.
Highlights
IntroductionThe SWCNT-FETs in double-gated structure have been fabricated by using a ferroelectric poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) polymer gate insulator to obtain the controllable hysteresis of drain current under different polarized states
The SWCNT-FETs in double-gated structure have been fabricated by using a ferroelectric poly (P(VDF-TrFE)) polymer gate insulator to obtain the controllable hysteresis of drain current under different polarized states
The P(VDF-TrFE) film is chosen as the top gate insulator due to its high dielectric constants[17], isolation effect of moisture[18] and polarization properties[19,20,21,22], which can compensate the current hysteresis arising from SWCNT networks and achieve a controllable hysteresis loop and threshold voltage of SWCNT channel under different polarized states
Summary
The SWCNT-FETs in double-gated structure have been fabricated by using a ferroelectric poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) polymer gate insulator to obtain the controllable hysteresis of drain current under different polarized states. The P(VDF-TrFE) film is chosen as the top gate insulator due to its high dielectric constants[17], isolation effect of moisture[18] and polarization properties[19,20,21,22], which can compensate the current hysteresis arising from SWCNT networks and achieve a controllable hysteresis loop and threshold voltage of SWCNT channel under different polarized states. The threshold voltage can be tuned to desired values quantitatively by applying bottom gate voltage to control the carrier concentration in SWCNT network channel under the electrostatic doping effect. We adopted the standard lithography process to achieve the graphics of organic polymers by dry etching process, which offers a great potential to the scaling down of the size of organic electronics and the compatibility with conventional CMOS process technology
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
