Considerations on the optimal power stage segmentation algorithm for MHz integrated synchronous Buck DC-DC converters

Abstract

For those MHz integrated synchronous Buck DC-DC converters (ISBC), a power stage segmentation technique might be applied for the sake of improving light load efficiency. The paper discusses the difference about efficiency in the case that losses contributions from Cds and Cgd in inactive power FET subcells are considered or not and indicates the existence of efficiency optimization's saturation effect in respect to the number of active power FET cells. After that, the paper presents the variation characteristics of power FET rdson using On-Semi SCN05 technology's eight manufacturing runs and temperature shift as two example cases. The variation of rdson implies that practical efficiency might deviate from an expected one, provided that the number of active power FET subcells is selected to be linearly proportional to the load current as that implemented in nowadays power FET width segmentation algorithms. Finally, the paper suggests a novel segmentation algorithm with automatic rdson compensation ability.