Abstract

We present a configurable 6T binary content-addressable memory (BCAM) and 12T ternary CAM (TCAM) which is based on conventional 6T SRAM bit cell. We also propose a match line (ML) voltage/current clamping scheme to reduce ML discharge delay considerably while preventing data corruption during CAM search operation compared to the previous configurable BCAM/TCAM using 6T SRAM bit cell. Experimental data from 4Kb (64×64b) CAM testchips in a 28nm CMOS technology shows that the proposed ML clamping scheme achieves 53.7% reduction in ML discharge delay compared to the previous word line underdrive scheme.

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