Concrete analysis of Schnorr-type signatures with aborts

Bugs, Stool, and the Irritable Bowel Syndrome: Too Much Is as Bad as Too Little?

The globalization of information exchange and the widespread introduction of information technologies in all spheres of society's life created the problem of protecting information processed in information systems from challenges and threats in the cybernetic space. The presence of important information in the functioning of the systems and critical national infrastructures objects enables its usage by the negatively-minded elements and groupings for the implementation of unlawful actions in the cyberspace by violating the integrity, availability, and confidentiality of information, and inflicting damage on information resources and information systems. In this case, the possibility of using information technologies in the cybernetic space in the interests of carrying out military-political and power confrontation, terrorism, and hacking cyber attacks are of particular concern. Today, intrusion detection and attack systems are usually software or hardware-software solutions that automate the process of monitoring events occurring in the information system or network, and independently analyze these events in search of security issues signs. An analysis of modern approaches to the development of such systems shows that it is the signature analysis of network traffic provides effective results in the development of protection modules of cyber systems. In addition, for the reliable protection of information systems, it is not only necessary to develop separate mechanisms of protection, but also to implement a systematic approach that includes a set of interrelated measures. The purpose of the article is to develop a system for recognizing cyber threats based on signature analysis, which would reduce the time of an attack detection of a cyber defense system while the number and complexity of cyber attacks are increasing

Compared to single signature analysis, checking multiple intermediate signatures has many advantages, e.g., smaller aliasing, easier computation of exact fault coverage, and shorter average test time. Conventionally, checking n signatures requires n references. Storing these references and comparing them with collected signatures imposes considerable hardware requirements. In this paper, we propose a novel multiple intermediate signature analysis scheme which checks n signatures against a single reference, thus making the circuitry for checking n signatures essentially the same as that for checking only one. The cost for implementing the proposed scheme is a very small nonrecurring CPU time expenditure in the design phase with no CUT modifications. In return, the proposed scheme yields significant recurring silicon area savings as well as reduced aliasing, and consequently higher test quality. This paper also defines a property for linear compactors that guarantees the existence of an initial state that necessarily yields two identical signatures at arbitrary check points for all circuits. >

A new generalized parallel signature analyzer with external Exclusive-OR gates (GPSA-EE) is presented. It allows the signature analyzer to have twice the number of inputs compared with an original parallel signature analyzer. The equivalence between a GPSA-EE and an SSA-EE (serial signature analyzer) is established. Using the concept of multiple signatures, the error detection capability of siguature analyzer can be enhanced by changing the connection between signature analyzer and circuit-under-test, or changing the characteristic polynomialp(x) of signature analyzer.

Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms

The paper presents an architecture for multiple input signature analyzers. The proposed signature analyzer with H/spl delta/ inputs is designed by parallelizing a GLFSR(/spl delta/,m), where /spl delta/ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by D.K. Pradhan and S. Gupta (1991), is a general framework for representing LFSR based signature analyzers. The parallelization technique described in the paper can be applied to any kind of GLFSR signature analyzer, e.g., SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with H/spl delta/ inputs requires less complex hardware than either single GLFSR(H/spl delta/,m)s or parallel construction H original GLFSR(/spl delta/,m)s. It is also shown that the proposed parallelization technique can be applied to a test pattern generator in BIST, since the GLFSR is also used to generate patterns for a CUT. The proposed technique would be practical for testing CUTs with a large number of input and output sequences, since the test circuit occupies a smaller area on the LSI chip than conventional test circuits.

There are only a few platforms that integrate multiple omics data types, bioinformatics tools, and interfaces for integrative analyses and visualization that do not require programming skills. Here we present iLINCS (http://ilincs.org), an integrative web-based platform for analysis of omics data and signatures of cellular perturbations. The platform facilitates mining and re-analysis of the large collection of omics datasets (>34,000), pre-computed signatures (>200,000), and their connections, as well as the analysis of user-submitted omics signatures of diseases and cellular perturbations. iLINCS analysis workflows integrate vast omics data resources and a range of analytics and interactive visualization tools into a comprehensive platform for analysis of omics signatures. iLINCS user-friendly interfaces enable execution of sophisticated analyses of omics signatures, mechanism of action analysis, and signature-driven drug repositioning. We illustrate the utility of iLINCS with three use cases involving analysis of cancer proteogenomic signatures, COVID 19 transcriptomic signatures and mTOR signaling.

The test response compression technique using signature analyzers or linear feedback shift registers (LFSRs) is discussed and some representative built-in self-test (BIST) designs which make use of LFSRs are presented. Signature analysis is a compression technique based on the concept of cyclic redundancy checking (CRC) and realized in hardware using LFSRs. The input to the LFSR is received from the output of a multiple input single output circuit under test (CUT). The structure and characteristics of LFSRs including a simplified mathematical analysis showing the confidence level in detecting faults are discussed. Some BIST design examples which include a programmable logic array, semiconductor memory, and a microcomputer are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Networks are regarded as one of the biggest advancements in the field of computer science. But they enable outsiders to “intrude” into our information. Intrusions can be in the form of simple eavesdropping, or gaining access to the host itself. Here, intruders are identified using two main methods – signature analysis and anomaly analysis. The proposed method is such that the signature analysis is strengthened by anomaly analysis, which in turn uses some level of intelligence based on the traffic parameters, obtained and processed using neural networks. The initial intelligence is obtained using the KDDCUP99 dataset, which trains a neural network. The neural network will take care of further detections, and it strengthens itself during the run itself. The result obtained suggests that even with minimal initial intelligence, iNIDS can reach accuracy levels of over 70%, and by increasing the initial set a little more, it reaches accuracy levels exceeding 80%.KeywordsIntrusion detectionneural networksintelligenceanomaly analysissignature analysisKDDCUP99JpCap

BIST is a system in which test patterns are generated to test the circuit. The circuit that needs to be tested is called circuit under test (CUT). If testing is done manually testing phase becomes more crucial one which consumes maximum amount of time and also not economically feasible when compared to the any other phase while fabricating the device or IC to overcome this problem BIST is used. This paper discusses design and implementation of BIST for testing the four bit combinational logic circuit and also the calculation golden signature value. The system consists of LFSR (Linear Feedback Shift Register), CUT (Circuit under Test), signature analyzer and a comparator. LFSR is a pattern generator which generates 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n-1</sup> combinations of test patterns, which are then applied to the CUT at the negative rising edge of the CLK. The output of the CUT is applied to the signature analyzer at positive edge of CLK1. Comparator compares the output of the signature analyzer with the golden signature value. If the output of comparator is equal to one, it implies that CUT is fault free if not there is fault present in CUT. Signature analyzer generates two distinct signature values for fault free CUT and faulty CUT.

Signature analysis provides a powerful heuristic method for the planning of simulation experiments and for the interpretation of simulation results. Signature analysis has been developed within the context of simulation of the dynamics of wafer fabrication operations in integrated circuit manufacturing. Graphical display of cycle time, throughput, and inventory provides a "signature" of the dynamic behavior of a given operation. Signatures of manufacturing operations are used to address several management issues. The effects of unplanned equipment failures are shown. The variation of signatures with initial inventory and with different time frames for management decisions is illustrated. The extension of signature analysis to other simulations is indicated.

Signature analysis has been used widely for fault detection as a part of Built-In Self Test (BIST). In this paper we show how signature analysis can be used not only for fault detection but also for identification of multiple errors produced by faults in the circuits under test. We construct Signature Analysis Registers (SARs) to detect and identify any specified number of errors in the input polynomials by choosing proper characteristic polynomials. To detect and identifyr errors in an input bit stream ofm bits, we use a polynomialg r (x)=1cm (f 1 (x), f 3 (x), ..., f 2r−1 (x)) as the characteristic polynomial for the SAR for any polynomialf 1 (x), where lcm represents the least common multiple of polynomials al $$fi(x) = Res_t (f_1 (t),x - t^i ), i = 3,...,2r - 1,$$ Res t denotes thet-Resultant, andm is less than the order off 1 (x). Given a faulty signature produced by an SAR constructed as described, we present an algorithm for the identification of the actual error bits in the input polynomial to the SAR. We also extend the use of BCH codes for error detection and correction to include nonprimitive polynomials.

On the relation of errors and its syndrome in signature analysis

Many test schemes use signature analyzers to compact the responses of a circuit under test. Unfortunately, there can be some faulty circuits with erroneous test responses but exactly the same signature as in the fault-free case. Hence, methods are required to determine how many faults become undetectable due to aliasing. Whereas previous work concentrated on combinational circuits, this paper investigates signature analysis for a wide range of sequential circuits, where the errors in successive responses are correlated. It is shown that for almost all faults of these circuits the probability of aliasing in a signature analyzer with k bits asymptotically approaches 2−k or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. The limiting value can be used as a good approximation for practical test lengths. These results are particularly useful for advanced built-in self-test techniques with low hardware overhead.

The paper describes several design considerations for single-board computers for improved field testability using signature analysis. It is shown that fault detection to major component level can be achieved by using signature analysers sampling the address and data bus of the unit under test. The signature analysers are synchronized to sample the buses during selected machine cycles only, so that the signatures taken characterize the operation of only one component. An example is given for implementation on Z80-based single-board computers.