Complementary heterostructure insulated gate FET circuits for high-speed, low power VLSI

Abstract

Complementary AlGaAs/GaAs Heterostructure Insulated Gate Field Effect Transistor (C-HIGFET) test circuits have been fabricated using MBE and a self-aligned ion-implantation process. Ring oscillators have been demonstrated with a minimum gate propagation delay of 76psec. Minimum stand-by power as low as 23 µW has been achieved in complementary RAM cells. Charge control models of HIGFETs including effects of gate current were implemented in UM-SPICE program to simulate the complementary circuits. Simulations show that the gate current in P- and N-channel devices plays a dominant role in determining the propagation delay and power consumption. The design (i.e. the optimum ratio of the N- and P-channel device widths) is also dependent on the gate currents as well as on the N-HIGFET threshold voltage, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tn</inf> . The lowering of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">tn</inf> from the present value of 0.9 V to 0.3 V should further decrease the gate propagation delay. Gate propagation delay close to 50 psec is estimated for a 1-micron C-HIGFET technology. Further improvements in speed and power dissipation can be achieved by increasing the AlAs molar fraction, decreasing the AlGaAs thickness, and going to submicron dimensions.