Abstract
This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.
Highlights
This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the digital-to-analogue converter (DAC)-based and the digital controller-based DCO in TSMC 65 nm CMOS technology
TheThe advantage of this system is is that the requires a minimal redesign from analogue to digital to adapt to that the voltage-controlled oscillator (VCO) requires a minimal redesign from analogue to digital Phase-locked loops (PLLs) to adapt to the the control voltage is given by the performance of these components control voltage thatthat is given by the the the performance of these components strongly depends on their analogue behaviour of the DAC, restricting advantage strongly depends on their analogue behaviour of the DAC, restricting the the keykey advantage of the digital system
The DAC-based DCO is designed with four digitally-controlled differential stages leading to a tuning range from 1.8 GHz to 2.2 GHz
Summary
Phase-locked loops (PLLs) are widely implemented in radio, wired and wireless telecommunication, clock generation, and other electronic applications. In contrast to an analogue PLL, digital PLLs consume less power and area while compromising linearity, as the generated frequency can only be varied in discrete steps limited by the resolution of the control bits [3]. A digital PLL suffers from several disadvantages in terms of jitter and phase-noise performance when compared to an analogue PLL. It decides the the overall performance, such as phase noise andand jitter, tuning range, power consumption, and the total occupied area. In this regard, two common types of DCO consumption, and the total occupied area. PLL to adapt to that the VCO requires a minimal redesign from analogue to digital PLL to adapt to the the control voltage is given by the DAC.
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