Comparative Study of p+/n+ Gate Modified Saddle Metal Oxide Semiconductor Field Effect Transistors and p+/n+ Gate Bulk Fin Field Effect Transistors for Sub-40 nm Dynamic Random Access Memory Cell Transistors

Abstract

We present a comparative study of p+/n+ gate modified saddle metal oxide semiconductor field effect transistors (MOSFETs) and p+/n+ gate bulk fin field effect transistors (FinFETs) that have been proposed for sub-40 nm dynamic random access memory (DRAM) applications. The p+/n+ gate structure consists of polycrystalline silicon (poly-Si) with two different work functions, so that the gate-induced-drain-leakage (GIDL) current of both devices can markedly be reduced. Device characteristics were carefully investigated in terms of on/off current ratio (Ion/Ioff) and subthreshold swing (SS) by changing fin body width (Wb), and we analyzed drain current–gate voltage (I–V) characteristics and electric field profiles of a 40 nm device by controlling n+ gate length (Ls). Finally, electrical characteristics with respect to gate length (Lg) are also compared.