Comparative study and implementation of BCD adders for reversible logic based ALU

Abstract

New technology innovation is facing a big challenge of miniaturization and low power electronics. Reversible logic proves to be an emerging solution. Reversible logic has various applications in modern low power computing environment. Adders play a major role in ALU and processors of any computing environment. Adders are not only suitable for addition but for subtraction and multiplication also. For many commercial applications, decimal arithmetic is highly demanding BCD adders. Therefore reversible logic based BCD adders need to be designed for the implementation of ALU to add on high speed and low power requirements. The existing BCD adders are synthesized and simulated in Verilog using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. Finally the results are compared for all existing BCD adders in terms of total number of ancillary input lines, total number of garbage output lines, number and types of reversible logic gate used and their associated quantum cost.