Comparative Assessment of Trap Charges Effect on Triple Hybrid Metal Gate Dielectric Modulated Junctionless Gate All Around Nanowire FET‐Based Biosensor

In this paper, a triple metal gate high-k gate all around junctionless nanowire field-effect transistor biotin biosensor has been developed to study the impact of different interface trap charges (ITCs) on device performance. The output characteristics, such as transconductance, drain current, total current density, and threshold voltage of proposed device have been examined. All results were authenticated using ‘‘atlas-3D’’ device simulation tool. Effect of interface trap charge on output characteristics, such as transconductance, switching ratio, leakage current, and total current density, including air and biotin biomolecule, have been studied. Drain-off current ratio was considered as a sensing metric for biotin biomolecule detection with different interface trap charges (ITCs). For instance, drain-off current results of biotin biomolecule in the presence of interface trap charge are \({3.12 \times 10}^{-12}\,\mathrm{A}\), \({2.10 \times 10}^{-13}\,\mathrm{A}\) and \({4.07 \times 10}^{-16}\,\mathrm{A}\) for positive, neutral, and negative interface trap charges, respectively. Finally, we have found that a negative ITC has a positive impact on our proposed biotin biosensor device performance than the positive ITCs, proving its efficacy for the detection of cardiovascular diseases in biomedical applications.

The current scenario in the semiconductor device area is well known to us all. In the last couple of decades, the downscaling of devices mainly focuses on field and voltage scaling. But here our area of discussion will be on field scaling because this affects the physical dimension of the devices including the channel length, channel thickness, oxide thickness, etc. As the thickness of the dielectric plays a crucial role in the operation of the field effect transistors, the scaling of oxide thickness remains in the spotlight for researchers. To meet the present industry demand, the conventional dielectric used as gate oxide, i.e., silicon dioxide (SiO2), turns as a porous sheet, which results in unwanted gate leakage current. So researchers are going for the high-k dielectric material to resolve this issue. Again, to achieve more gate control over the channel and hence to minimize the majority of short channel effects (SCEs), researchers and industry professionals are turning to multi-gate devices. Unlike single-gate devices, multi-gate structure has to be designed with a higher number of oxide layers corresponding to each gate electrode. This results in a higher number of interface layers or, in other words, larger area of interface between the oxide and the semiconductor region. However, the trapping of charges in the oxide region or oxide semiconductor interface needs to be discussed in detail, with consideration of high-k, for further improvement of our devices. There are mainly two types of charge trapping involved that we need to discussed in oxide layer for FET application purpose: (i) interface trap charges (ITCs) and (ii) oxide charges (OC). If we try to distinguish between these two charges, the gate bias can be very informative for this, because the interface trap charges vary with the gate applied field whereas the oxide charges not. Oxide charge can be categorized predominantly in three types on the basis of their technological importance, namely interface charge sheet (Qf), oxide trapped charges (Qot), and mobile ionic charge (Qm). Here we need to know the significance of each type, so we shall start with their definition. Our first type of charge as mentioned above can be identified as the remaining charge density after the annealing procedure. This is usually located at or very close to the interface of dielectric and semiconductor. The Qot can be found at the gate metal and oxide interface, and also can spread over the entire oxide region. The third and last type, i.e., mobile ionic charge, is introduced to the dielectric only through the alkali metal gate electrode. Hence these are usually present at the metal and oxide interface at no gate bias and all over the dielectric region at the biasing stage. Analysis and optimization of unwanted charge cloud present over the high-k dielectric region in multi-gate devices are more important than in single-gate devices. If we consider designing a multi-gate structure, we need to introduce a higher number of dielectric layers with respect to the number of gates. Trap charges creation or presence in these layers influences the channel behavior such as inversion layer build-up, threshold voltage roll-off, gate leakage current, etc. Again, in memory-based design, these dielectric materials sometime have more relaxation current due to the defects created during the fabrication or operation. Fabrication of these layers is more complicated than the conventional SiO2, and hence choosing an appropriate material for specific application can be vital. The above-discussed traps can sometime outweigh gate control even in multi-gate devices, especially for low-power design. Now the primary focus of our discussion will be on how these charges affects the capacitance of MOS capacitor and FETs operation, and hence the selection of our high-k dielectric for future scaling of our multi-gate designs and their application.

In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I–V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.

Investigation on electrical parameters between single and double material gate nanoribbon FETs including trap distributions

The trapping of positive and negative charges in silicon dioxide was studied as a function of injection current density and pulse width during dynamic high-field/high-current stress. Trapping of negative charges in oxide under dynamic stress conditions was found to give an accumulated charge to breakdown (Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bd</inf> ) that was independent of stressing current density if the total injected charge per pulse was kept constant. However, the trapping of positive charges increased significantly as current density was increased. Under dynamic stress with fixed current density, the trapping of negative charge in the oxide increased with increasing pulse width while the trapping of positive charge was independent of pulse width. The experimental data for dynamically stressed devices suggest a strong correlation between the breakdown of thin oxides and the amount of negative charge trapped in them.

Performance investigation and impact of trap charges on novel lateral dual gate oxide-bilateral tunnelling based field effect transistor

With sub-10nm node technology approaching fast, counteracting short channel effects (SCEs), sub-threshold conduction, reducing transistor off-current and gate leakage current have become aspects of real concern. Integration of III-V semiconductors in multigate device architectures has become a topic of intense research and study for low power logic implementation [1]. Multigate device architectures like FinFETs, GAA FETs provide better control over channel carrier accumulation and improved short channel performance over planar structures. Recently, In0.53GA0.47As Quantum-Well (QW) Tri-Gate MOSFET with bi-layer high-k dielectrics of Al2O3/HfO2 has been reported with channel width and height scaled down to 30nm and 20nm respectively and gate length scaled down to 60nm [2]. In this work, we present a simulation study of inversion Capacitance-Voltage (C-V) and Threshold (VTH) characteristics of a III-V tri-gate device (Fig.1 inset) using self-consistent modeling. The device structure used for modeling in this study incorporates 2nm Al2O3 with In composition kept at 0.7 in the undoped InGaAs QW channel. The In0.52Al0.48As back barrier thickness is kept at 60nm. In this study TiN has been used as the gate metal. In all these studies, temperature is considered to be fixed at 300K. Finite Element Method (FEM) has been used to solve Schrodinger-Poisson equations in a coupled manner applying proper boundary conditions, using COMSOL Multiphysics and MATLAB, taking into account wave function penetration and other quantum mechanical effects. 2D Schrodinger equation is solved using effective mass approximation and open boundary condition to determine electron wave functions and eigen states in the quantum well. Using carrier wave functions in the tri-gate channel, inversion carrier concentration is determined by applying 1D density of states and Fermi-Dirac distribution function. The effect of fixed oxide charges, interface trap charges and oxide border trap charges is not taken into account. The developed simulator is also benchmarked with the simulation results obtained for a III-V GAA nanowire transistor [3]. A quantum definition of threshold voltage for multigate FETs is available in literature [4]. According to this definition, the threshold voltage can be presented as a combination of classical and quantum terms. Here, peak electron concentration npeak(x,y) and average electron concentration navg are used to define threshold voltage of the device. At threshold point, the profile of npeak(x,y)/navg would show a change in slope which results from shift in carrier accumulation as device operation moves from subthreshold to inversion mode [4]. In this study, same definition of threshold voltage has been used. The simulation reveals strong carrier accumulation at the corners of the oxide/semiconductor interface which is expected for multigate device structures (Fig. 1). The simulation also reveals strong subband quantization in the QW channel (Fig. 2). Occupied subbands below the Fermi level contribute to the carrier concentration. As the device dimension is shrunk, volume inversion effect becomes more and more significant and carriers begin to accumulate at the middle portion of the tri-gate channel. This phenomenon leads to an increase in carrier concentration in the middle portion of the QW fin as channel dimension is scaled (Fig. 3). This phenomenon shifts channel formation towards the middle portion of the tri-gate QW fin. Simulation also reveals higher inversion capacitance at lower In composition in the channel which may be attributed to higher density of states effective mass at lower In composition (Fig. 4). Although variation of top gate oxide thickness reveals effect on inversion capacitance, the threshold voltage remains mostly unchanged with top gate oxide thickness. Study of variable channel dimension while keeping WFin=HFin reveals lower carrier accumulation in the device cross section per unit channel length which may lead to lower inversion capacitance with lower channel dimension (Fig. 5). Lowering channel dimension results in stronger quantum confinement and subband splitting which eventually leads to an increase in threshold voltage (Fig. 6). Lowered In composition in the channel also increases threshold voltage of the device (Fig. 6). In this work, a simulation study of a III-V tri-gate quantum well device for 10nm technology and beyond is presented. The outcome of this work would be useful in the implementation of III-V multigate device structures for high speed and low power logic applications.

Integration of stoichiometric molybdenum trioxide (MoO 3−x ) as an effective hole transport layer (HTL) in solar cells is expected to reduce fabrication cost by eliminating the high temperature processes while maintaining high conversion efficiency. In this work we performed a systematic study to extract the electronic properties of vapor-phase deposited MoO 3−x thin film and MoO 3−x /crystalline silicon interface through capacitance and conductance analysis. Effect of MoO 3−x thickness as well as post deposition annealing on series resistance, electrical response, interface and bulk trapped oxide charges were profoundly examined and determined. Moreover, variation in series resistance, behavior of the interface and bulk trapped charges were revealed. Finally, frequency and bias voltage dependence of the series resistance and interface trapped charge were determined

Distinction between triple gate (TG) and double gate (DG) silicon-on-insulator (SOI) FinFETs is presented here on the basis of their electrostatic and transport characteristics. A study missing in previous works on DG and TG FinFETs is the characterization of these structures with respect to the variation of top oxide thickness. In fact an exact value of the top-oxide thickness that can differentiate DG FinFETs from TG ones has not been reported yet. From this perspective, electrostatic and transport characteristics of DG and TG FinFETs having sub-10 nm fin dimensions are investigated in this work as a function of the top oxide thickness. To duly incorporate the quantum-mechanical (QM) effects in such nanoscale regime of operation, the devices are simulated by self-consistently solving the coupled Schrodinger's and Poisson's equations. Simulation results suggest that DG and TG FinFETs can be differentiated by a parameter which we define in our work with respect to the surface potentials existing beneath the top and side gates. This finding in effect proposes a critical top oxide thickness of FinFET that can draw the distinction between its DG and TG variants. The results also indicate that deposition of top oxide layer beyond a limit does not bring about any significant change in the electrostatic and transport characteristic of DG FinFETs in the ballistic limit.

Evaluating the performance of triple and double metal gate charge plasma transistors for applications in biological sensors at a dual cavity location

In the present work, the reliability issues of GaAs/Al2O3 Junctionless FinFET have been investigated by considering interface trap charges at semiconductor/oxide interface. RF/Analog performance of GaAs/Al2O3 Junctionless FinFET has been studied by evaluating different figures of merit such as drain current, Ion/Ioff ratio, transconductance, output conductance, capacitance (gate to source) and cut-off frequency. To analyze the effect of temperature on trap charges, the simulation study has been done at 300, 400 and 500 K temperature. In addition to this, a comparative analysis between GaAs/Al2O3 and Si/SiO2 Junctionless FinFET has also been carried out using a 3D device simulator (ATLAS). The results express that GaAs/Al2O3 Junctionless FinFET shows better performance in terms of the Ion/Ioff ratio and gives better immunity to trap charges as compared to Si/SiO2 Junctionless FinFET.KeywordsJunctionless FinFET (JL FinFET)Short channel effects (SCEs)Trap charges

Semiconductor-oxide (Si-SiO 2 )interface trap charges come into existence during the fabrication process of device because of various types of damages like hot electron stress and radiation damage. These trap charges change the device electrical properties thereby adversely affecting the circuit performance. In this paper the effect of localized trap charges on a Junction less Double gate P-MOSFET are investigated. The influence of different charges (positive and negative)for different charge density profiles of trap charges on surface potential, drain current and threshold voltage are analyzed to evaluate the reliability of device. In the present work SILVACO 3-D ATLAS device simulator have been used for simulation.

By accounting for the effects of equivalent oxide charges on the flat-band voltage, a novel interface-trapped-charge-degraded subthreshold current model is presented for the quadruple-gate (QG) MOSFETs based on the quasi-3-D scaling equation and Pao-Sah's integral. It indicates that a thin gate oxide can effectively reduce the subthreshold current degradation caused by the trapped charges. In contrast to the thin gate oxide, a thick silicon film is required to alleviate the subthreshold current degradation caused by the negative trapped charges. For the short-channel behavior, the damaged device with negative and positive trapped charges can decrease and increase subthreshold current roll up caused by the short-channel effects, respectively. Due to computational efficiency, the model can be easily used to explore the hot-carrier-induced current behavior for the fully depleted QG MOSFETs for its memory cell application.

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship Ids–Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage Ctot–Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

The equipment and devices which are long-time running in space are affected by space radiation effects and hot carrier injection effects at the same time which would reduce their optional times. Normally, the single mechanism test simulation method is used on the ground simulation test but the multi-mechanism effect affects the space equipments and devices, including total irradiation dose effect, hot carrier injection effect, etc. The total dose dependence of hot carrier injection (HCI) effect in the 0.35 m n-channel metal oxide. semiconductor (NMOS) device is studied in this paper. Three samples are tested under different conditions (sample 1# with total irradiation dose (TID) and HCI test, sample 2# with TID, annealing and HCI test, sample 3# only with HCI test). The results show that threshold voltage of NMOS device with 5000 s HCI test after 100 krad (Si) total dose radiation has been negatively shifted then positively during total dose irradiation test and HCI test, and the threshold is higher than that of the device without radiation test. But the threshold voltage shift of NMOS device with 5000 s HCI test and 200 h annealing test after TID test is higher than that of the devices without radiation test and lower than that of the devices without annealing test. That is, the parameters of NMOS device vary faster with the combined effects (including the total dose irradiation effect and HCI effect) than with single mechanism effect. It is indicated that the hot electrons are trapped by the oxide trap charges induced by irradiation effect and then become a recombination centre. And then the oxide trap charges induced by irradiation effect reduce and become negative electronic. The interface trap charges induced by irradiation effect are reduced and then increased it is because the electrons of hole-electron pairs in the Si-SiO2 interface are recombined by oxide traps in the oxide during the forepart of HCI test but then the electrons are trapped by interface traps in the Si-SiO2 interface because the electrons from source area are injected to interface during the HCI test. So the threshold voltage is positively shifted due to the negative oxide trap charges and interface trap charges. The association effect is attributed to the reduction of oxide traps induced by recombination with hot electrons and the increase of the interface traps induced by irradiation trapped hot electrons.