Abstract
For the original article see ibid., vol.SC-21, no.3, p.430-5 (1986). A CMOS four-quadrant multiplier based on 12 transistors was proposed by K. Bult and H. Wallinga in the above-titled paper using four floating-well transistors to keep V/sub T/ constant. It is shown analytically by the commenter that the floating wells can be avoided with little penalty on distortion, but with reduction in signal output. A four-transistor multiplier is also analyzed. >
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