Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation

Abstract

Several approaches have been proposed to early analyze the functional impact of a set of faults in a digital circuit, for a given application. These methods start with the RT-level description of the circuit and aim either at classifying the faults according to their main potential effect, or at analyzing more in depth the error propagation paths in the circuit. This paper discusses the advantage of combining the two types of analyses, on the basis of extensive SEU-like fault injections performed on a VHDL model of the 8051 micro-controller. The results show that this combination allows a designer to pinpoint critical locations, easing to improve hardening. The impact of the workload on the analysis is also discussed. It is shown that in the case of a general purpose processor, the internal error configurations leading to a failure can be very dependent on the application program; taking the application into account may therefore lead to a simpler and cheaper hardening of the circuit. The quality of the obtained results with respect to the number of injection experiments is also discussed. In a lot of cases, the injection of a very small percentage of all possible faults already gives very significant information to the designer.