Co-Packaged Optics - Heterogeneous Integration of Chiplets (Switch, Photonic IC, and Electronic IC)

The rapid growth of artificial intelligence (AI), data centers, and high-performance computing (HPC) has increased the demand for large bandwidth, high energy efficiency, and high-density optical interconnects. Co-packaged optics (CPO) technology offers a promising solution by integrating photonic integrated circuits (PICs) directly within or close to electronic integrated circuit (EIC) packages. This paper explores the evolution of CPO performance from various perspectives, including fan-out wafer level packaging (FOWLP), through-silicon via (TSV)-based packaging, through-glass via (TGV)-based packaging, femtosecond laser direct writing waveguides, ion-exchange glass waveguides, and optical coupling. Micro ring resonators (MRRs) are a high-density integration solution due to their compact size, excellent energy efficiency, and compatibility with CMOS processes. However, traditional thermal tuning methods face limitations such as high static power consumption and severe thermal crosstalk. To address these issues, non-volatile neuromorphic photonics has made breakthroughs using phase-change materials (PCMs). By combining the integrated storage and computing capabilities of photonic memory with the efficient optoelectronic interconnects of CPO, this deep integration is expected to work synergistically to overcome material, integration, and architectural challenges, driving the development of a new generation of computing hardware with high energy efficiency, low latency, and large bandwidth.

We are delighted to introduce a Special Issue on Optical Interconnects for the IET Optoelectronics magazine. This issue presents the current status as well as some of the outstanding progress that has been witnessed in the rapidly evolving area of optical interconnects. Today, data centres (DC) and high-performance computers are struggling with limited interconnect capacity and increased power consumption while trying to meet overwhelming bandwidth demands. As photonics technologies have been rapidly maturing, optical interconnects have come into the spotlight as the means to cope with the emerging bandwidth, energy, and capacity needs. As such, a wealth of photonic interconnect solutions across the DC hierarchy has unfolded, covering from electro-optic boards to transceiver development, on-chip and on-board switches and interconnects as well as novel noninvasive monitoring methods for light controlling for compensating thermal crosstalk, fabrication tolerances and unstable environmental conditions. At the same time, the increased penetration of optical interconnects in short-reach communications, such as board and chip levels, has triggered new challenges in photonics technologies calling for new innovations with respect to integration techniques and packaging methods. This Special Issue of IET includes integrated circuits, assembly techniques, systems-level architectures, and controlling methods related to short reach ‘chip-to-chip’, ‘in-the-box’, and ‘box-to-box’ communications. Specific areas covered by this special issue include: Silicon photonic transceiver technologies and flat DC topologies; High-speed electro-optic hosting boards and fast, energy-efficient electronics; DC switches and co-packaged optic (CPO) technologies; and Noninvasive controlling techniques for complex photonic integrated circuits. The four papers in this special section promote high-performance optical interconnect architectures and key technologies to tackle the rising bandwidth demands of DCs. They cover (a) co-packaged DC optics, (b) silicon technology transceiver modules and high-speed hosting boards for multisocket server board (MSB) interconnects and (c) automated controlling architecture for complex photonic systems; Items (b) and (c) draw from impressive achievements accomplished through the recently completed European H2020 Project ICT-STREAMS. This report written by C. Mickenberg tries to shed light on motivating factors behind co-packaged optics (CPO), the trade-offs involved and their potential impact on data centre network architectures. The article reviews the evolution of DC switch application-specific integrated circuit (ASICs) and DC optics, provides a future road map and finally discusses the potential impact of CPO on the network architecture. This topic is covered by two articles. The first, written by M. Morallis-Pegios, proposes using silicon photonics to advance interconnect throughput, socket connectivity and energy efficiency in MSB layouts by enabling a flat-topology wavelength division multiplexing (WDM) point-to-point optical MSB interconnect scheme. WDM silicon photonic transceivers coassembled with their electronic circuits achieving a 50-Gb/s line rate and 400-Gb/s aggregate data transmission are demonstrated. The article also proposes silicon photonic Arrayed Waveguide Grating Router (AWGRs) that can offer collision-less time-of-flight connectivity for up to 16 nodes. The second article covering that area is written by T. Lamprecht and reports on the development of electro-optic hosting boards for on-board transceiver subassemblies which is required to eventually form the Tb/s multi-socket onboard communication. The article also discusses the electrical interface as well as photonic board requirements, including the manufacturing technique and the assembly concept that was followed to deliver terabyte per second multichip optical communication. This article, written by F. Zanetto, introduces a novel dithering technique for real-time control of multiple cascaded photonic integrated devices, proposing a calibration-free strategy to support the development and real-life diffusion of increasingly complex photonic systems. The article elaborates on the implementation of a calibration-free automated control loop exploiting integral controllers to close a real-time feedback and stabilise the optimum working point of the employed photonic devices. The effectiveness of the proposed architectural approach is experimentally validated with the error-free routing and transmission of a 30-Gbit/s optical signal traversing a cascade of micro-ring resonator filters. All of the articles selected for this Special Issue present a wide variety of key topics and significant results addressing optical interconnects in high-performance data communication systems, including new progress on architectures, systems and packaging techniques as well as novel optimised controlling methods. As guest editors, we would like to thank all of the authors for their high-quality submissions that significantly contribute to the optical interconnect field. We would also like to thank the reviewers for their valuable and constructive technical comments that greatly enhance the Special Issue, because their feedback and comments ensure the high quality of the IET Optoelectronics Journal. We hope that this IET Special Issue will provide a useful reference of the state-of-the-art in optical interconnects to readers, and we anticipate such technological perspectives will stimulate new advancements and technological outcomes that will in turn enrich the growing field of optical interconnects. This work was supported by the E.C. through the H2020-ICT-STREAMS research project (688172).

The trends in co-packaged optics (CPO) will be investigated in this study. Emphasis is placed on the heterogeneous integration of photonic integrated circuit (PIC) and electronic IC (EIC). In particular, two-dimensional (2D) and three-dimensional (3D) heterogeneous integration of application specific IC (ASIC) switch, PIC, and EIC w/o bridges, and heterogeneous integration of ASIC switch, PIC, and EIC on glass substrate will be discussed. Some recommendations will be provided.

Co-packaged optics (CPO) and three-dimensional (3D) optoelectronics represent a new frontier in high-speed data communication, targeting the rising demands for bandwidth, energy efficiency, and low latency in data centers, artificial intelligence (AI), and high-performance computing (HPC). This review examines the progression from pluggable optics to integrated photonic solutions, highlighting breakthroughs in silicon photonics, heterogeneous integration, and advanced packaging methods such as 2.5D interposers, Embedded Multi-die Inter- connect Bridge (EMIB), and 3D stacking. These innovations promise significant reductions in power consumption and notable gains in bandwidth density, yet thermal management, manufacturing yields, and alignment precision remain key challenges. Applications span hyperscale data centers, quantum networks, automotive lidar, and aerospace communications, illustrating the wide-reaching impact of these emerging technologies. The paper concludes by emphasizing future research directions and collaborative efforts needed to address remaining barriers and fully harness the transformative potential of integrated photonic- electronic systems.

The technological essence of silicon photonic integrated circuits is to utilize the mature complementary metal oxide semiconductor (CMOS) technology, or the processes compatible with CMOS technology, to monolithically integrate various kinds of photonic devices in silicon-on-insulator (SOI) substrate. The technology of silicon photonic integrated circuits can fabricate large-scale integrated photonic devices for mass production, providing innovative solutions to the ever-growing demands of high bandwidth, low manufacturing cost, low power consumption in data center, high performance computing center, artificial intelligence and cloud storage. Highspeed optical transceiver modules based on silicon photonic integrated circuits have been commercialized in recent years. Moreover, co-packaged optics (CPO) has become a hot topic and trend for the assembly solution of next generation high-speed switch, and is expected to replace the hot-pluggable optical transceiver modules in the near future.

We study the network locality improvements that can be achieved by using co-packaged optics in data center and high-performance computing (HPC) networks. The increased escape bandwidth offered by co-packaged optics can enable switches with speeds of 51.2 Tb/s and beyond. From a network architecture perspective, the key advantages of introducing co-packaged optics at the switch points include the implementation of large-scale topologies of > 12,000 end points with 4 × higher bisection bandwidth and the reduction of the required number of switches by > 40 % compared with state-of-the-art approaches. From a network operation perspective, improved network locality and faster operation can be achieved since the higher-radix switches can mitigate the impact of network contention. Placing applications under fewer leaf switches reduces the number of packets that cross the spine switches in a leaf-spine topology. The proposed scheme is evaluated via discrete-event simulations: we initially evaluate the network locality properties of the system by using virtual-machine traces from a production data center, and we subsequently quantify the performance improvements by simulating an all-to-all pattern for a variety of message sizes over a number of nodes. The results suggest that co-packaged optics form a promising solution for keeping up with bandwidth scaling in future networks. The virtual-machine analysis shows that large-scale applications can be placed under up to 50% fewer first-level switches, while the network analysis shows speedups of up to 7.1, which translates to execution time reductions of up to 26% and 42.7% for applications with communication ratios of 0.3 and 0.5, respectively.

Driven by the increasing demand for faster high-performance computing (HPC) networks and higher data center fabric transmission bandwidth, to favorite the needs of machine learning, data training, and computing, the adoption of co-packaged optics (CPO) and near-packaged optics (NPO) is one of the innovations to mitigate the slowing down of Moore's law. Because of the high temperature generated by the next generation of high-speed chips like switch ASICs, CPUs, and GPUs, coupling fibers to photonic integrated circuit (PIC) with traditional epoxy-based fiber arrays is becoming more challenging and problematic. Therefore, an epoxy-free bonding method using femtosecond laser welding borosilicate glass 3.3 and optical fibers is proposed and demonstrated. Then, a low loss and polarization independent fiber to fiber coupling was demonstrated to show the reliability of bonding. In the experiment, a V groove is used for aligning and positioning two fibers. After welding, the minimum coupling loss and polarization dependent loss is 0.347 dB and below 0.1 dB respectively. The average shear force limit of the welded samples with 0.5 mm welding length is measured to be as high as ∼0.719 N. This technology could be used for epoxy-free based edge coupling the high density multi-fibers with PIC and has potential of scalable manufacturability through automation.

We investigate the advantages of using co-packaged optics for building low-diameter, large-scale high-performance computing (HPC) and data center networks. The increased escape bandwidth offered by co-packaged optics can enable high-radix switch implementations of more than 150 switch ports, which can be combined with data rates of up to 400 Gb/s per port. From the network architecture perspective, the key benefits of using co-packaged optics in future fat-tree networks include (a) the ability to implement large-scale topologies of > 11 , 000 end points by eliminating the need for a third switching layer and (b) the ability to provide up to 4 × higher bisection bandwidth compared to existing solutions, reducing at the same time the number of required switch application-specific integrated circuits by > 80 % . From the network operation perspective, both reduced energy consumption and lower packet delays can be achieved since fewer hops are required; i.e., packets need to traverse fewer serializer/deserializer lanes and fewer switch buffers, which reduces the probability of contending with other packets and improves the tolerance of network congestion. The performance of the proposed architecture is evaluated via discrete-event simulations for a wide range of representative HPC synthetic-traffic cases that include both hotspot and non-hotspot scenarios. The simulation results suggest that co-packaged optics form a promising solution to keep up with bandwidth scaling in future networks, while the reduced number of switching layers can lead to significant mean packet delay improvements that start from 30% and reach up to 74% for high-load conditions.

The recent exponential growth of AI/ML workloads, hyperscale data centers, and high-performance computing has intensified the demand for co-packaged optics (CPO), which integrate optics and electronics to overcome the bandwidth and power limitations of traditional pluggable transceivers. However, adoption of CPO requires reliable, detachable fiber-to-chip interconnects which must be compatible with high-volume manufacturing and packaging processes. Current solutions face significant challenges, including sub-micron alignment accuracy, reflowability, and repeatability/interchangeability across mating cycles, all while meeting high-volume manufacturing requirements. This paper analyzes bottlenecks in detachable fiber-to-chip interconnects for CPO systems and presents key technologies to enable connectors with high-performance detachment capability. Experimental results demonstrate a detachable FAU achieving <0.2 dB (3σ) repeatability and <0.6 dB (3σ) interchangeability. Furthermore, we describe a path for wafer-level packaging that can address cost-efficiency and scalability, paving the way for high-volume manufacturing readiness. These advances establish a roadmap for CPO commercialization, enabling next-generation data centers to meet AI-driven bandwidth demands.

High bandwidth demanding applications such as high-performance computing and hyperscale datacenters are drivers for co-packaged optics, which aims to bring optical signals as close as possible to the electrical computing chips by integrating the electro-optic transceivers and ASICs on the same package substrate. These next-generation switches require advanced fiber-to-chip connectivity and novel packaging concepts to enable sufficient power and cost savings. As such, low-loss, high bandwidth, and high fiber-counts are required at the photonic chip interface. In this work, these challenges are addressed by enabling the multi-fiber push-on (MPO) interface at the edge of integrated glass waveguide substrates and thus leverages the existing fiber connector eco-system. An ultrafast laser process is used to singulate glass wafers into individual photonic chips leaving optical-quality end-facets with <1 μm flatness over the 6.5 mm wide connector region thereby directly enabling low-loss fiber-to-chip edge-coupling. To overcome the high-costs and complex photonic packaging associated with active alignment of the fiber connectors to the glass waveguide interfaces, ultrafast laser-ablated features are accurately positioned on the glass substrate to enable self-alignment of the MPO connector guide-pins resulting in a passive alignment approach. Subsequent mating and de-mating of the MPO connector to the glass waveguide interface yields on average a 0.19 dB increase in the coupling loss compared to using active alignment.

Integrated photonics is essential in Radio Access Networks (RAN). For example, current pluggable optics and upcoming co-packaged optics (CPO) rely on it to increase capacity and energy efficiency. In addition, Photonic Integrated Circuits (PIC) may perform in future processing functions such as radiofrequency (RF) generation and mixing. This paper provides a comprehensive review of the current and future applications of integrated photonics to radio systems. It starts with the most mature technology (pluggable optics), discussing the challenges to meet the demand for the increase of bandwidth (BW) density expected with the Sixth mobile Generation (6G). Then, it moves to more advanced short reach interconnection technologies, based on CPO and optical Printed Circuit Boards (PCB). These technologies will allow to meet that demand, provided that certain RAN-specific developments, discussed in the paper, are undertaken. The potential of Artificial Intelligence (AI) to further improve the energy efficiency of short reach optical interconnects is also shortly introduced. Finally, Micro-Wave Photonics (MWP) techniques to process the RF signal in the optical domain are presented. The paper elaborates on their potential to improve the performance of radio systems and on the challenges remaining to move these techniques from lab to market. As a conclusion, integrated photonic technologies will expand their role in the evolution of radio systems, but with a variable timescale depending on their degree of compatibility with existing production processes.

A technology of co-packaged optics, which is mounting photonics integrated circuits and electronic integrated circuits on the same board, is essential to meet the demands of high-capacity transmission in data centers. In this respect, polymer optical waveguides have attracted much attention because of mechanical stability, excellent processability, and compatibility with electronic circuits. To achieve high-capacity optical transmission, we are developing a new package substrate, which we call active optical package (AOP) substrate, as a solution of co-packaged optics. The AOP substrate consists of a conventional organic package substrate such as glass-epoxy substrates, on which silicon photonics dies are embedded and SMF connectors are mounted. In the AOP, the silicon photonics inputs/outputs (I/Os) and the optical connectors are connected by 3D optical wiring technology that has a function of converting the pitch size. The 3D optical wiring is realized with a pair of micro-mirrors and a single-mode polymer waveguide. First, we have evaluated the high-speed optical transmission performance of a single-mode polymer optical waveguide for LAN-WDM network. We observed there was no noticeable penalty for optical transmission for all LAN-WDM channels. And then, we demonstrate transmission of an AOP substrate comprising of silicon waveguide, two micro-mirrors and polymer waveguide. Transmission of 112-Gb/s PAM4 optical signal was performed without noticeable penalty up to 85 °C.

Modern artificial intelligence and high-performance computing systems face critical bottlenecks in inter-chip communication as computational capabilities continue to advance beyond the limits of traditional copper-based interconnects and board-edge optical modules. Co-packaged optics emerges as a transformative solution by integrating photonic components directly within processor packages, dramatically reducing electrical path lengths and enabling unprecedented bandwidth densities while lowering energy consumption per transmitted bit. This article presents a comprehensive hybrid integration architecture that combines two-and-a-half-dimensional and three-dimensional packaging techniques to co-locate photonic chiplets with compute dies on silicon interposers. The article leverages micro-ring resonator-based wavelength division multiplexing on silicon photonic platforms to achieve high aggregate throughput while maintaining compatibility with advanced logic manufacturing processes. Through detailed co-design of packaging structures, electrical-optical interfaces, thermal management systems, and control algorithms, the architecture addresses key technical challenges that have historically impeded photonic integration efforts. Validation through multi-level simulations and physical prototypes demonstrates feasibility for rack-scale optical connectivity meeting the demanding requirements of distributed machine learning workloads. The article examines critical parameters that affect the timing of commercial adoption, such as manufacturing yield, serviceability, the need for standardization, and economic trade-offs. Results indicate that hybrid co-packaged optics architectures provide viable pathways for sustaining bandwidth scaling in next-generation data center fabrics serving artificial intelligence applications.

Recently, the desired very high throughput of 5G wireless networks drives millimeter-wave (mm-wave) communication into practical applications. A phased array technique is required to increase the effective antenna aperture at mm-wave frequency. Integrated solutions of beamforming/beam steering are extremely attractive for practical implementations. After a discussion on the basic principles of radio beam steering, we review and explore the recent advanced integration techniques of silicon-based electronic integrated circuits (EICs), photonic integrated circuits (PICs), and antenna-on-chip (AoC). For EIC, the latest advanced designs of on-chip true time delay (TTD) are explored. Even with such advances, the fundamental loss of a silicon-based EIC still exists, which can be solved by advanced PIC solutions with ultra-broad bandwidth and low loss. Advanced PIC designs for mm-wave beam steering are then reviewed with emphasis on an optical TTD. Different from the mature silicon-based EIC, the photonic integration technology for PIC is still under development. In this paper, we review and explore the potential photonic integration platforms and discuss how a monolithic integration based on photonic membranes fits the photonic mm-wave beam steering application, especially for the ease of EIC and PIC integration on a single chip. To combine EIC, for its accurate and mature fabrication techniques, with PIC, for its ultra-broad bandwidth and low loss, a hierarchical mm-wave beam steering chip with large-array delays realized in PIC and sub-array delays realized in EIC can be a future-proof solution. Moreover, the antenna units can be further integrated on such a chip using AoC techniques. Among the mentioned techniques, the integration trends on device and system levels are discussed extensively.

The rapid evolution of artificial intelligence (AI) and its high-performance demands on computational systems have significantly impacted modern data center infrastructure. Conventional scaling strategies are approaching physical and economic limits, necessitating innovations in system-level design and networking technologies. Photonics has emerged as a transformative solution, offering unparalleled bandwidth, energy efficiency, and scalability across multiple layers of data center architecture. This paper explores the adoption of photonic technologies, including co-packaged optics (CPO), optical circuit switches (OCS), and silicon photonics in general, to address critical challenges in interconnect bandwidth, latency, and power consumption. By analyzing their integration at the package, rack, and network levels, we highlight how photonics can overcome the limitations of traditional electronic solutions, paving the way for the next generation of AI infrastructure.