CMOS Logic Gates Leakage Modeling Under Statistical Process Variations

Abstract

In the history of semiconductor, transistor scaling has been used as a primary method to improve IC performance. However in the nanometer regime, aggressive scaling is reaching its limits and the control of semiconductor manufacturing process is becoming increasingly difficult. Variations in manufacturing process have grown, and variations in device parameters have grown even more, resulting in wider distributions which, in turn, could result in yield loss [1]. Another scaling consequence has been a drastic increase of leakage currents. Leakage has become a major contributor to the total IC power, reducing battery life during stand-by operations in portable applications. Furthermore, this is worsen by the very large impact of variations on device leakage. In the nanometer regime the four major contributors to transistors leakage are: the subthreshold leakage (Ids), the gate leakage (Igd), the reverse-biased drain and source substrate junction band to band tunneling (Ibtbt), and the gate induced drain leakage (Igidl). Each of those leakage currents becomes significant in nano-scaled devices tightening the constraints of nowadays digital designs [2].