CMOS BASED ARCHITECTURE FOR HIGH SPEED BCD ADDITION

Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 times slower than binary arithmetic implemented in hardware. Therefore, hardware support for decimal arithmetic is required. In this paper, a reduced delay binary coded decimal (BCD) adder is proposed. The proposed adder improves the delay of BCD addition by increasing parallelism. On the critical-path of the proposed BCD adder, there are two 4-bit binary adders, a carry network, one AND gate, and one OR gate. To make area and delay comparison, the proposed adder and previously proposed five decimal adders are implemented in VHDL and synthesized using 0.18 micron TSMC ASIC library. Synthesis results obtained for 64-bit addition (16 decimal digits) show that the proposed BCD adder has the shortest delay (1.40 ns). Furthermore, it requires less area than previously proposed three decimal adders.

Applications that cannot tolerate the loss of accuracy that results from binary arithmetic demand hardware decimal arithmetic designs. Binary arithmetic in Quantum-dot cellular automata (QCA) technology has been extensively investigated in recent years. However, only limited attention has been paid to QCA decimal arithmetic. In this paper, two cost-efficient binary-coded decimal (BCD) adders are presented. One is based on the carry flow adder (CFA) using a conventional correction method. The other uses the carry look ahead (CLA) algorithm which is the first QCA CLA decimal adder proposed to date. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The proposed CFA-based BCD adder has the smallest area with the least number of cells. The proposed CLA-based BCD adder is the fastest with an increase in speed of over 60% when compared with the previous fastest decimal QCA adder. It also has the lowest overall cost with a reduction of over 90% when compared with the previous most cost-efficient design.

Financial and business applications utilize decimal information and invest the majority of their energy in decimal number-crunching. Programming usage of decimal number-crunching is common, at any rate, multiple times slower than paired math actualized in equipment. This paper proposes a reduced delay binary coded decimal (BCD) adder that improves BCD addition delay by expanding parallel processing. The ordinary BCD adders are delayed because of the utilization of two binary adders. we structured and executed a new double mode BCD adder which utilizes just a single adder that produced the sum and sum+6. Using a pipeline procedure, an additional 128-bit BCD adder was implemented. The proposed BCD adder was planned and implemented using VHDL with XILINX 9.2 modification. The sequences of the regular BCD adder contrast with the proposed BCD adder. Experimental results show that the proposed BCD adder is 16.7% quicker than a traditional BCD adder. The proposed BCD 128-bit adder is 61.2% faster than the regular BCD 128 adder.

This paper presents two universal 4×4 ‘reversible RPS gates’ that can function as a reversible 4-bit Binary to BCD converter with a garbage count of zero. The new ‘fully or partially reversible RPS gate’ gives an optimized design of the offset correction circuit of a reversible Binary Coded Decimal (BCD) adder. The paper proposes reversible implementations of BCD adder using fully reversible RPS gates and using combination of HNC-RPS (fully and partially) gates; and the comparisons are tabulated. The HNG-RPS designs achieve a reduction in garbage outputs and logical complexity compared to the existing reversible BCD adder designs. This can form the basic building block of a high speed decimal ‘Arithmetic and Logic Unit (ALU)’ for a low power reversible ‘Central Processing Unit (CPU)’.

Background: In the field of high-speed digital circuits, the efficiency of Binary Coded Decimal (BCD) adders consists of significant importance in optimizing the speed of arithmetic operations in computing systems. BCD arithmetic is crucial in scientific and financial computing systems that require decimal accuracy. Objectives: This study examines the performance of BCD adders as designed using two different logic families, Complementary Metal Oxide Semiconductor (CMOS) and dynamic logic. CMOS logic which is meant to have low static power dissipation and dynamic logic which is meant to have high-speed switching capabilities and reduced transistor count. Methods: A new dynamic logic realization of a high-speed BCD adder improved from the previously introduced CMOS-based BCD adder is presented in this work. Dynamic logic design keeps the same pull-down network as the equivalent CMOS but with a precharge PMOS and an evaluate NMOS transistor. This design is implemented under 45nm technology and is optimized for a single digit BCD adder. Schematics are made using DSCH, and Verilog files were developed which are simulated using MICROWIND 3.9. The delay and power dissipation values are obtained with an operating voltage of 1V, and a parametric analysis was conducted comparing delay, and power dissipation for varied temperatures in the range (-40°C to 120°C). Findings: The findings depict enhanced performance of dynamic logic implementation compared to static CMOS implementations with reduced power dissipation and increased switching speed due to the inherent benefits of dynamic logic. Novelty: For comparison purpose this work also implements two different adders along with the static CMOS logic implemented adder which are already present in literature. The final results depict that dynamic logic implemented adder outperforms all the three adders with a power delay product (PDP) of 14.75 fJ when compared to 72.07 fJ, 80.48 fJ, and 50.92 fJ PDP of other works. Keywords: BCD adder, CMOS logic, Dynamic logic, Pull down network, Precharge, Evaluate, Parametric analysis, Delay, Power dissipation, Power delay product (PDP)

Quantum-dot Cellular Automata (QCA) technology presents a promising avenue for the realization of ultralow-power and high-speed digital circuits owing to its inherent quantum properties and nanoscale dimensions. In this study, a novel design and analysis of a binary-coded decimal (BCD) adder implemented using QCA technology is proposed. The BCD adder is a fundamental component of digital arithmetic circuits and is widely applied in various computational systems, including calculators, processors, and digital signal processors. Leveraging the unique features of QCA, such as the absence of current flow and the potential for highly compact layouts, we present a detailed design methodology for the BCD adder circuit, including the implementation of basic QCA gates and construction of the BCD addition logic. Performance metrics, such as area, delay, and power consumption, were evaluated through extensive simulations using QCA Designer, QCA design, and a simulation tool. The Ripple Carry Adder (RCA) is one of the major blocks in the BCD circuit and a prominent factor in determining the area and delay of the circuit. Therefore, an efficient full adder was used to design an RCA with less area and delay. Clocking in a QCA impacts the polarization state of a QCA cell, and this scheme is utilized efficiently to achieve novelty. The proposed design occupies 15.625% less area, and the cell count is reduced by 11.55% compared with the existing state-of-the-art design. Power dissipation reports were obtained using the QCA Pro tool, which briefly describes the average leakage and average dissipation energy of the total circuit, and a spectrum to depict the energy dissipation of each cell in the circuit. The results demonstrate the feasibility and efficiency of the proposed BCD adder design in QCA technology, demonstrating its potential for realizing energy-efficient and high-performance digital arithmetic circuits. This work contributes to the growing body of research on QCA-based digital circuit design and lays the groundwork for the further exploration of QCA technology in practical computing applications.

In this paper, we have proposed a design technique for the reversible circuit of binary coded decimal (BCD) adder. The proposed circuit has the ability to add two 4-bits binary variables and it transforms the addition into the appropriate BCD number with efficient error correcting modules where the operations are reversible. We also show that the proposed design technique generates the reversible BCD adder circuit with minimum number of gates as well as the minimum number of garbage outputs.

Decimal arithmetic is gaining prominence in many commercial applications where a high degree of accuracy is desired. Some of these include currency conversion and internet based financial transactions. This paper explores various weighted Binary Coded Decimal (BCD) coding schemes to find one efficient representation that can be used to design a hardware and delay efficient BCD adder. Out of the wide range of possibilities, some representations are more desirable than the others because of certain inherent properties they possess. This paper summarizes the properties that make a particular BCD representation more attractive than others to implement a decimal adder. It is found that one of the 4221 encoding schemes possesses most of these properties. Finally, it also provides the design and implementation of a multi-digit decimal adder using the best coding scheme. The implementation is on a Spartan 3E FPGA chip. The proposed design is compared with an excess-three adder which is one of the fastest adders using alternative coding methods.

The world of computing is in transition. As chips become smaller and faster, they dissipate more heat, in turn more energy is consumed. Reversible logic is gaining significance in the context of emerging technologies such as quantum computing. Reversible circuits have one-to-one mapping between the inputs and outputs. Hence, there is no loss of energy. Reversible circuits are of high interest in low-power CMOS design, optical computing, nano technology, and quantum computing. In this work, we present designs of reversible Binary Coded Decimal (BCD) adder and unified reversible BCD addition/subtraction circuit. We propose three design approaches for BCD addition. The proposed designs 1 and 2 are aimed at optimizing Garbage Outputs. The proposed design 3 outperforms in all the performance parameters along with producing zero Garbage Outputs compared to proposed designs 1 and 2. We present [Formula: see text] digit reversible BCD addition/subtraction circuit using proposed design 3 for BCD addition to get the benefit of performance parameter optimization. This design outperforms existing counterparts.

In recent years, reversible logic has become one of the most important areas of researches because of its applications in several technologies; such as low-power CMOS, Nano-computing and optical computing. In this paper, we have presented designs of a compact and efficient fault tolerant reversible Binary Coded Decimal (BCD) adder as well as a fault tolerant reversible Carry Skip BCD adder. We have proposed new reversible fault tolerant gates and heuristic algorithms to design compact BCD Adders. The proposed reversible fault tolerant BCD adder achieves the improvement as reducing cost of 23.07% on the number of gates, 52.67% on quantum cost, 31.03% on garbage outputs, 29.16% on the number of constant inputs and 23.07% on unit delay over the existing best one. Similarly, the proposed reversible fault tolerant carry skip BCD adder achieves the improvement as reducing cost of 34.72% on the number of gates, 43.24% on quantum cost, 37.5% on garbage outputs, 37.14% on the number of constant inputs and 34.72% on unit delay over the existing best one.

In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders can be implemented in a wide array of applications such as financial and commercial computations as most of the data stored and calculated are in decimal format. Hardware implementation of a BCD adder has been known to perform at least 100 times faster than its software counterparts. Current trends in reversible BCD adder consist of 4 major parts — 4-bit Adder, Correction and Detection Unit, and Modified 4-bit Adder. Designs were chosen based on overall design quantum cost, complexity, and estimated delays. The designs are then implemented on Altium Designer using Hardware Description Language(HDL) and verified on Xilinx Spartan 3AN and Altera Cyclone I FPGAs.

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.

A parallel decimal multiplier with improved performance is proposed in this paper by exploiting the properties of three different binary coded decimal (BCD) codes, namely the redundant BCD excess-3 code (XS-3), the overloaded decimal digit set (ODDS) code and the BCD-4221/5211 code. The signed-digit radix-10 recoding is used to recode the BCD multiplier to the digit set [-5, 5] from [0, 9]. The redundant BCD XS-3 code is adopted to generate the multiplicand multiples in a carry-free manner. The XS-3 coded partial products (PPs) are converted to ODDS PPs to fit binary partial product reduction (PPR). In this paper, a regular decimal PPR tree using ODDS and BCD-4221/5211 codes is proposed; it consists of a binary PPR tree block, a non-fixed size BCD-4221 counter block and a BCD-4221/5211 PPR tree block. The decimal carry-save algorithm based on BCD-4221/5211 is used in the PPR tree to obtain high performance multipliers. Moreover, an improved PPG circuit and an improved parallel prefix/carry-select decimal adder are proposed to further improve the performance of the proposed multipliers. Analysis and comparison using the 45 nm technology show that the proposed decimal multipliers are faster and require less hardware area than previous designs found in the technical literature.

This paper proposes a new enhanced Single Digit BCD Adder (SDBA) to perform decimal addition optimally. Quantum‐dot Cellular Automata (QCA) will construct nanostructured arithmetic circuits for future computing. One of the vital structures in arithmetic structures is the Binary Coded Decimal (BCD)/Decimal Adder. The existing Decimal Adders require many cells and consume more delay, which makes the circuit inefficient in doing decimal addition faster. The binary adder structures are more significant in deciding the performance of conventional BCD adders. Multiplexers are used in the proposed BCD adder to enhance the speed with less complexity. The main contribution of the proposed SDBA design is to replace the final part of the conventional structure Carry Flow Adder (CFA) based BCD adder with a multiplexer, which improves the speed and increases the regularity of the structure. The multiplexers perform the binary to decimal sum conversion in parallel rather than the carry rippling in the lower part of the standard circuit. The SDBA uses the optimized CFA Type‐II binary adder and new logic with a 2:1 multiplexer. Furthermore, the proposed BCD adder is an optimized design in terms of delay, which requires 2.75 clock cycles only compared to the recent designs. © 2025 The Author(s). IEEJ Transactions on Electrical and Electronic Engineering published by Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.

Reversible logic is one of the emerging computational methodologies which assures zero power dissipation through theoretical laws of thermodynamics. It has received significant interest in application on quantum computing, nanotechnologies and low power computing devices. In this work, we present a reversible logic implementation for Binary Coded Decimal (BCD) adder which is designed to obtain lowest quantum cost value. Other parameters such as ancilla input, garbage output and delay are kept at minimal. Experiment result shows that the proposed work outperforms other designs in terms of quantum cost. Considering for a 1 digit BCD adder, it has a 4% improvement in terms of quantum cost compared to the current best existing ones. The improvement range increases as the BCD digit becomes larger.