以CMOS 0.35微米製程實現之70~500 MHz50%工作週期修正電路與頻域量測技術

Abstract

A 50% duty-cycle correction (DCC) circuit is reported in this thesis. The proposed DCC circuit consists of a clock generator and a delay detector. The clock generator is edge-triggered by the input and produces an output whose pulse width is adjusted to half of the signal period by the delay detector. Meanwhile, the input phase information is maintained. The proposed new DCC circuit has many features, including a wider acceptable duty-cycle range of the input clock, a larger operating frequency, synchronizing output phase with input phase. The circuit is implemented in a 0.35-μm CMOS process. To evaluate the output duty-cycle accuracy, a single-sideband mixing test method is adopted. This circuit operates from 70 MHz to 500 MHz, and accommodates duty cycles ranging from 5% to 95% at 500 MHz. The output signal is corrected to 50% ± 1.4%. Operated from a 3.3-V supply, the circuit dissipates 2 mA at 70 MHz and the circuit dissipates 7 mA at 500 MHz. This fully-integrated DCC chip area is 1.1 mm*1.1 mm, including pads, mixer, and an on-chip loop capacitor (100 pF), the core area is 0.5 mm*0.55 mm.