Abstract
Electrical contacts on the top surface of solar cells and light emitting diodes cause shadow losses. The phenomenon of extraordinary optical transmission through arrays of subwavelength holes suggests the possibility of engineering such contacts to reduce the shadow using plasmonics, but resonance effects occur only at specific wavelengths. Here we describe instead a broadband effect of enhanced light transmission through arrays of subwavelength metallic wires, due to the fact that, in the absence of resonances, metal wires asymptotically tend to invisibility in the small size limit regardless of the fraction of the device area taken up by the contacts. The effect occurs for wires more than an order of magnitude thicker than the transparency limit for metal thin films. Finite difference in time domain calculations predict that it is possible to have high cloaking efficiencies in a broadband wavelength range, and we experimentally demonstrate contact shadow losses less than half of the geometric shadow.
Highlights
The wire circumference to the wavelength is x ≪ 1), under normal incidence, and away from resonance, the scattering amplitudes for light polarized parallel to the wire Tp and transversal to the wire Tt can be approximated to[15]: Tp
Where θ is the scattering angle, n = nw/ni is the relative refractive index, nw is the refractive index of the wire, ni is the refractive index of the incidence medium, x = πwni/λ is the size parameter, w is the wire diameter, and λ is the free space wavelength
In the small size limit, and in the absence of resonances, metal nanowires become invisible, a fact that can be used to advantage in the design of top contact grids for solar cells and light emitting diodes (LEDs)
Summary
FDTD simulations were performed using Lumerical FDTD Solutions software. The typical line width, height and geometric shadow factor used in concentrator solar cells are 3 μm, 600 nm and 3% respectively[10]. Reactive ion etching (RIE) in a Oxford Plasmalab 80 by means of a CHF3 plasma was performed to transfer the line pattern to the device surface through the iCON-16 and photoresist/SiOx layers. For the Ag short period arrays, details of this plasma etching process include: chamber pressure, 19 mTorr; RIE power, 100 W; wafer temperature, 30 °C; output DC Bias, ~275 V This etch was stopped with a thin layer (20 nm) of SiOx at the bottom of the trench to protect the GaAs. In the gold wire arrays, verticality of the side walls was improved by using a pulsed etch with an on/off cycle of 30 s/120 s, with N2 flow in the first off minute, as well as using a lower pressure (5 mTorr), higher power plasma (200 W, 475V). The grid sheet resistance was measured by the four point probe method with a high precision current source and a separate nanovoltmeter
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