Chiplet Architectures: Enabling Scalable Integration for the AI Era

In this paper, research priorities and demands of future products for heterogeneous system integration technology are presented. Heterogeneous Integration technologies ensures the integration of different functionalities such as signal processing, sensors, actuators, photonics, power, and coolers, that is specifically adopted to the application environments. Heterogeneous integration technologies are bridging the gap between nanoelectronics and the application system.

Technologies for Heterogeneous Integration - Challenges and chances for fault isolation

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

PurposeHuman-induced marine environmental noise, such as commercial shipping and seismic exploration, is concentrated in the low-frequency range. Meanwhile, low-frequency sound signals can achieve long-distance propagation in water. To meet the requirements of long-distance underwater detection and communication, this paper aims to propose an micro-electro-mechanical system (MEMS) flexible conformal hydrophone for low-frequency underwater acoustic signals. The substrate of the proposed hydrophone is polyimide, with silicon as the piezoresistive unit.Design/methodology/approachThis paper proposes a MEMS heterojunction integration process for preparing flexible conformal hydrophones. In addition, sensors prepared based on this process are non-contact flexible sensors that can detect weak signals or small deformations.FindingsThe experimental results indicate that making devices with this process cannot only achieve heterogeneous integration of silicon film, metal wire and polyimide, but also allow for customized positions of the silicon film as needed. The success rate of silicon film transfer printing is over 95%. When a stress of 1 Pa is applied on the x-axis or y-axis, the maximum stress on Si as a pie-zoresistive material is above, and the average stress on the Si film is around.Originality/valueThe flexible conformal vector hydrophone prepared by heterogeneous integration technology provides ideas for underwater acoustic communication and signal acquisition of biomimetic flexible robotic fish.

Ever since IBM pioneered microelectronics packaging, IBM Research has continued to innovate to ensure that packaging and heterogeneous integration technology is available to satisfy the needs for performance, complexity, and memory and logic density with regard to high performance computing systems. In this era of ever-expanding need for high-performance computing and ever-pervasive artificial intelligence, traditional scaling economics headwinds combined with the need for versatility and fast product development mandate a system-level approach to generate the efficiencies the industry has been able to provide in the past through more traditional scaling approaches. This system-level approach renders imperative the use of chiplet-based architectures and the use of heterogeneous integration and advanced packaging to achieve the disaggregation with best-performing and most efficient IP components to sustain a viable economic model while achieving performance targets. In this talk we will discuss several key process and integration considerations that drive the use of various horizontal and vertical interconnection technology elements that must be implemented to enable the successful realization of efficient and cost-effective high-performance systems in the AI era. Future progress on these technology fronts will depend on disruptive innovation in two critical areas: (a) wafer-level and die-level processes, such as lithographic patterning, wafer-wafer bonding and debonding, bond and assembly processes, etc. that can enable packaging of these heterogeneous structures without compromising performance and reliability, (b) commensurate improvements and enablement of adequate metrology and inspection solutions to address the challenges stemming from these new chiplet-interconnecting methods and the associated topographic implications.

Heterogeneous devices integration technologies constitute one of most promising driving forces of system integration as they enhance the system performance of electronics products. Currently, many technologies for heterogeneous devices integration have been reported [1]-[2]. The heterogeneous devices integration technologies that have been reported are mainly implemented for SoC (System on Chip) by applying the advantages of process compatibility between the devices. However, it has been impossible to integrate them in the case that the processes are incompatible. Also, many integration technologies applying SiP (System in Package) technology with the interposer substrate have been reported. However, SiP technology, it has been impossible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced heterogeneous devices integration technology is required. In the previous work, pseudo-SoC realized by a wafer-level heterogeneous devices system integration technology, which incorporates MEMS and CMOS-LSI, has been studied to verify the validity [3]-[6]. In the work, the flexible pseudo-SoC for mobile terminal application was also verified [5]. Furthermore, in the previous work, high-density pseudo-SoC of AFE (Analog Front End) for Smart-health-care Intelligent Life Monitor Engine & Eco-system (Silmee <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> ) application was developed [7]-[8]. In the application, 2 kinds of pseudo-SoC of AFEs which are for ECG (Electrocardiogram) and for Pulse were developed. However, developed pseudo-SoC of AFE has not sufficient density because the 2 kinds of pseudo-SoC of AFE occupy a large area in the Silmee engine. This paper describes the pseudo-SoC which integrated AFE circuit of ECG and Pulse in one microchip for Silmee application that incorporates several types of heterogeneous devices.

The advent of digital microfluidic lab-on-a-chip (LoC) technology offers a platform for developing diagnostic applications with the advantages of portability, increased automation, low-power consumption, compatibility with mass manufacturing, and high throughput. However, most digital microfluidic platforms incorporate limited optical capabilities (e.g., optical transmission) for integrated sensing, because more complex optical functions are difficult to integrate into the digital microfluidic platform. This follows since the sensor must be compatible with the hydrophobic surfaces on which electrowetting liquid transport occurs. With the emergence of heterogeneous photonic component integration technologies such as those described herein, the opportunity for integrating advanced photonic components has expanded considerably. Many diagnostic applications could benefit from the integration of more advanced miniaturized optical sensing technologies, such as index of refraction sensors (surface plasmon resonance sensors, microresonator sensors, etc.). The advent of these heterogeneous integration technologies, that enable the integration of thin-film semiconductor devices onto arbitrary host substrates, enables more complex optical functions, and in particular, planar optical systems, to be integrated into microfluidic systems. This paper presents an integrated optical sensor based upon the heterogeneous integration of an InGaAs-based thin-film photodetector with a digital microfluidic system. This demonstration of the heterogeneous integration and operation of an active optical thin-film device with a digital microfluidic system is the first step toward the heterogeneous integration of entire planar optical sensing systems on this platform.

This paper presents the recent important developments in multilayer/3D multichip module and heterogeneous integration technologies, utilizing the advantages of a variety of semiconductor and advanced integration and packaging technologies, towards making the next-generation mmW and sub-mmW/THz wireless applications feasible and affordable. This includes advanced multilayer ceramic-based thick-film based technique which has realized high-performance and compact passive components to complete modules, achieving the highest performance in MCMs, using a cost-effective mounting and integration technique, yet covering frequencies from 1 to 200 GHz. Moreover, presents the recent advancements in 3D wafer-level heterogeneous integration technology (to 300 GHz), which combines compound-semiconductor (InP/GaN) with Si/CMOS for challenging mmW/sub-mmW applications.

We demonstrate a novel Ultra-Precise Deposition (UPD) technology for heterogeneous integration in advanced packaging and printing interconnections on flexible substrates. UPD allows maskless deposition of highly-concentrated pastes on complex substrates. The printing resolution is in the range from 1 to 10 µm. The ink viscosity is up to 2,500,000 cP, which corresponds to 85% wt. of metal content and the electrical conductivity of printed structures is up to 45% of the bulk value. This technology is designed for rapid prototyping and manufacturing of next-generation printed and flexible electronics devices, including sensors, integrated circuits, displays, and energy harvesting systems.

Heterogeneous integration has attracted much attention for high performance computing (HPC) since artificial intelligence (AI) accelerators surged. The technologies for heterogeneous integration, such as silicon interposer (2.5D), fan-out wafer-level-packaging (FOWLP), and organic substrate, have been proposed to integrate logic-logic or logic-HBM chips in the AI system for performance and cost benefits. However, the tremendous data flow in 5G era requires higher data rate and bandwidth for the extensive die-to-die communication. Therefore, a BEOL-scale re-distributed layer (RDL) technology should be developed to satisfy the requirements. In this paper, a novel ultra-high-density InFO (InFO_UHD) technology with submicron RDL is developed to provide high interconnect density and bandwidth for logic-logic system. The bandwidth density can achieve record high 10 Tbps/mm at line width and spacing (L/S) of 0.8/0.8 um and length of 500 um, for a logic-logic system using simplified IO driver. Using the technology in logic-memory system, we found that the scaling of RDL thickness, L/S, and dielectric thickness can mitigate ring-back problems in the eye diagram of organic substrate. Given HBM2 specification, the bandwidth density can achieve more than 0.4 Tbps/mm from dramatically improved signal integrity. Finally, power efficiency, in the metric of energy per bit, of the interconnect technology under simplified IO driver and HBM2 driver condition was calculated and compared with other technology, respectively.

This thesis describes a series of experiments and fabrication methods on high-aspect-ratio 3D microstructures for wafer level packaging and 3D heterogeneous system integration (3D-HSI) using novel materials such as carbon nanotubes and thick-film photo-resists. Furthermore, theoretical and experimental research efforts are made to understand the mechanical material behaviour when scaling down towards the nanometer scale. Heterogeneous system integration combines different silicon dies and materials into a single microelectronic package. It enables cost effective and reliable approaches to achieve more functionality (“More than Moore”) and minimization of geometric size and power consumption. Vertical Interconnect Access (VIAs) are key for 3D system integration, leading towards smaller systems and shorter overall interconnect length.

Advanced FOPoP technology in heterogeneous integration: Finite element analysis with element birth and death technique

Technologies for heterogeneous integration have been promoted as an option to drive innovation in the semiconductor industry. However, adoption by designers is lagging behind and market shares are still low. Alongside the lack of appropriate design tools, high manufacturing costs are one of the main reasons. Micro-transfer printing (μTP) is a novel and promising micro-assembly technology that enables the heterogeneous integration of dies originating from different wafers. This technology uses an elastomer stamp to transfer dies in parallel from source wafers to their target positions, indicating a high potential for reducing manufacturing time and cost. In order to achieve the latter, the geometrical interdependencies between source, target and stamp and the resulting wafer utilization must be considered during design. We propose an approach to evaluate a given μTP design with regard to the manufacturing costs. We achieve this by developing a model that integrates characteristics of the assembly process into the cost function of the design. Our approach can be used as a template how to tackle other assembly-related co-design issues – addressing an increasingly severe cost optimization problem of heterogeneous systems design.

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry to realize the system integration. In this paper, we will discuss the new trend of advanced packaging technology — a strong need for application-specific integration solutions. Many of those are proposed. The solution with higher performance at lower cost will prevail. Furthermore, the solutions that readily integrate multi-chip to enable chip-partition to extend Moore's Law effectively have long-term advantages.